ITC 1996:
Washington,
DC,
USA
Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996.
IEEE Computer Society 1996, ISBN 0-7803-3541-4 BibTeX
@proceedings{DBLP:conf/itc/1996,
title = {Proceedings IEEE International Test Conference 1996, Test and
Design Validity, Washington, DC, USA, October 20-25, 1996},
publisher = {IEEE Computer Society},
year = {1996},
isbn = {0-7803-3541-4},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Plenary
Session 2.0:
Automatic Test Generation
Session 3.0:
BIST:
Architectures and Generation
Session 4.0:
New Test Considerations for Mixed-Signal Devices
Session 5.0:
Topics in Test Hardware
Session 6.0:
Practical and Higher-Level Fault Simulation
- Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski:
A Universal Technique for Accelerating Simulation of Scan Test Patterns.
135-141 BibTeX
- Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz:
On Potential Fault Detection in Sequential Circuits.
142-149 BibTeX
- Weiwei Mao, Ravi K. Gulati:
Improving Gate Level Fault Coverage by RTL Fault Grading.
150-159 BibTeX
- Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham:
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor.
160-166 BibTeX
Session 7.0:
BIST Pattern Generation
Session 8.0:
Testing of Asynchronous Circuits
Session 9.0:
Industry Impact:
Screeninig,
Test,
and Measurement Breakthroughs
- Timothy R. Henry, Thomas Soo:
Burn-in Elimination of a High Volume Microprocessor Using IDDQ.
242-249 BibTeX
- Peter C. Maxwell, Robert C. Aitken, Kathleen R. Kollitz, Allen C. Brown:
IDDQ and AC Scan: The War Against Unmodelled Defects.
250-258 BibTeX
- Alan W. Righter, Jerry M. Soden, Richard W. Beegle:
High Resolution IDDQ Characterization and Testing - Practical Issues.
259-268 BibTeX
- K. Ozaki, H. Sekiguchi, S. Wakana, Y. Goto, Y. Umehara, J. Matsumoto:
Novel Optical Probing System with Submicron Spatial Resolution for Internal Diagnosis of VLSI Circuits.
269-275 BibTeX
Session 10.0:
Fault Simulation and Diagnosis of Delay Faults
Session 11.0:
Memory Test:
Design for Testability
- Piero Olivo, Marcello Dalpasso:
Self-Learning Signature Analysis for Non-Volatile Memory Testing.
303-308 BibTeX
- Anne Meixner, Jash Banik:
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique.
309-318 BibTeX
- Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.
319-324 BibTeX
Session 12.0:
Board Test Challenges and Solutions
Session 13.0:
Delay-Fault Testing 1
Session 14.0:
Microprocessor Test
Session 15.0:
An Evolving Mixed-Signal Boundary-Scan Standard
Session 16.0:
Delay-Fault Testing 2
Session 17.0:
Software for New Test Strategies
Session 18.0:
Innovations in Current Testing
Session 19.0:
Mixed-Signal DFT and Fault Simulation
Session 20.0:
DFT:
Inching Forward with Partial-Scan Design
Session 21.0:
Test Languages and Tools
Session 22.0:
Application of SPC to IC Design,
Manufacturing and Test
Session 23.0:
New Techniques for Realistic Faults
Session 24.0:
Design-for-Testability Inspirations
Session 25.0:
High Frequency and Timing in ATE
Session 26.0:
Topics in Test Engineering
Session 27.0:
System Test:
Practical Aspects,
Partitioning and Simulation
Session 28.0:
Test Synthesis Solutions
Session 29.0:
Advanced Fault Modelling Techniques
Session 30.0:
Test Economic Issues
Session 31.0:
MCM Test:
Methods and Applications
Session D1.0:
Design Validation:
Methodologies and Case Studies
- Carl Pixley, Noel R. Strader, W. C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen:
Commercial Design Verification: Methodology and Tools.
839-848 BibTeX
- Marc E. Levitt:
Formal Verification of the UltraSPARCTM Family of Processors via ATPG Methods.
849-856 BibTeX
- Neeta Ganguly, Magdy S. Abadir, Manish Pandey:
PowerPCTM Array Verification Methodology using Formal Techniques.
857-864 BibTeX
Session D2.0:
Hybrid Validation and Test Techniques
Session D3.0:
Design Validation:
From System Specification to Process Effects
Session L1:
Unpowered Opens Testing
- Kenneth P. Parker:
Introduction ITC 1996 Lecture Series on Unpowered Opens Testing.
924 BibTeX
- Ted T. Turner:
Capacitive Leadframe Testing.
925 BibTeX
- Jack Ferguson:
High Fault Coverage of In-Circuit IC Pin Faults with a Vectorless Test Technique Using Parasitic Transistors.
926 BibTeX
- Joe Wrinn:
Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test, and Radio Frequency Induction Test.
927 BibTeX
- Anthony J. Suto:
Analog AC Harmonic Method for Detecting Solder Opens.
928 BibTeX
- Stig Oresjo:
Unpowered Opens Test with X-Ray Laminography.
929 BibTeX
Session L2:
Practical Aspects of IC Diagnosis & Failure Analysis:
A Walk Through the Process
Panel 1:
Why Do We Talk about DFT When the Problem is Bad Design and Bad CAD Tools?
Panel 2:
Asynchronous Design:
Nightmare or Opportunity?
Panel 5:
DFT for Embedded Cores
Panel 6:
What Are the Next Generation Test Methodologies for Board and System Test?
Panel 7: Will I-DDQ Testing Leak Away in Deep Sub-Micron Technology?
Copyright © Sat May 16 23:26:42 2009
by Michael Ley (ley@uni-trier.de)
