DFT 2007:
Rome,
Italy
Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba (Eds.):
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy.
IEEE Computer Society 2007, ISBN 0-7695-2885-6 BibTeX
Session 1 - Reliable NoCs and SoCs
Session 2 - Single Event Effects
- Hossein Asadi, Mehdi Baradaran Tahoori, Chandra Tirumurti:
Estimating Error Propagation Probabilities with Bounded Variances.
41-49
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- Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube:
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.
50-58
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- Rani S. Ghaida, Payman Zarkesh-Ha:
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model.
59-67
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- Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena:
SET Emulation Under a Quantized Delay Model.
68-77
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Session 3 - Defect and Fault Tolerance
- Andrea Manuzzato, Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Luca Sterpone, Massimo Violante:
Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs.
79-86
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- Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio:
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs.
87-95
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- Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante:
Optimization of Self Checking FIR filters by means of Fault Injection Analysis.
96-104
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Session 4 - Fault Injection and Reliability Analysis
- Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Sandro Pastore, Giacomo R. Sechi, Roland Weigand:
Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform.
105-113
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- Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Riccardo Mariani:
A Functional Verification Based Fault Injection Environment.
114-122
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- Riccardo Mariani, Peter Fuhrmann:
Comparing fail-safe microcontroller architectures in light of IEC 61508.
123-131
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- Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto:
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip.
132-141
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Interactive Poster Session
- Yoon-Hwa Choi, Myeong-Hyeon Lee:
A Defect-Tolerant Molecular-Based Memory Architecture.
143-151
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- Martin Straka, Jiri Tobola, Zdenek Kotásek:
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.
152-160
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- Ravi Bonam, Yong-Bin Kim, Minsu Choi:
Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture.
161-169
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- Michele Favalli:
Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth.
170-178
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- Mehdi Kamal, Somayyeh Koohi, Shaahin Hessabi:
Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs.
179-187
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- Mojtaba Valinataj, Saeed Safari:
Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction.
188-196
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- Piotr Zajac, Jacques Henri Collet:
Production Yield and Self-Configuration in the Future Massively Defective Nanochips.
197-205
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- Anjela Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikoleva:
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs.
206-214
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- Waleed Al-Assadi, Sindhu Kakarla:
Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design.
215-222
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- Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu:
Timing-Aware Diagnosis for Small Delay Defects.
223-234
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Session 5 - Testing and Design for Testability
- Irith Pomeranz, Sudhakar M. Reddy:
A-Diagnosis: A Complement to Z-Diagnosis.
235-242
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- Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.
243-251
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- Abhijit Jas, Srinivas Patil:
Analysis of Specified Bit Handling Capability of Combinational Expander Networks.
252-260
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- Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky:
Reduction of Fault Latency in Sequential Circuits by using Decomposition.
261-271
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Session 6 - Soft Errors
- Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao:
Soft Error Hardening for Asynchronous Circuits.
273-281
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- Takashi Ikeda, Kazuteru Namba, Hideo Ito:
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.
282-290
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- Jorge Luis Lagos-Benites, Davide Appello, Paolo Bernardi, Michelangelo Grosso, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda:
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.
291-300
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Session 7 - Defect and Fault Tolerance
Session 8 - Dependable Solutions for Memories and Storage
Session 9 - Reliable Design Techniques
Session 10 - Emerging Technologies - 1
Session 11 - Testing
Session 12 - Emerging Technologies - 2
Session 13 - Reliable Applications
- Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle:
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections.
499-507
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- Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar:
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.
508-516
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- Jozsef Dudas, Michelle L. La Haye, Jenny Leung, Glenn H. Chapman:
A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects.
517-525
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- Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren:
Quantitative Analysis of In-Field Defects in Image Sensor Arrays.
526-534
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Copyright © Sat May 16 23:06:36 2009
by Michael Ley (ley@uni-trier.de)
