7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore.
IEEE Computer Society 1998, ISBN 0-8186-8277-9 BibTeX
@proceedings{DBLP:conf/ats/1998,
title = {7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {1998},
isbn = {0-8186-8277-9},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Address
BIST I
High-Level Synthesis
- Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara:
A High-Level Synthesis Method for Weakly Testable Data Paths.
40-45
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- Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
Alleviating DFT Cost Using Testability Driven HLS.
46-51
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- Fabian Vargas, E. Bezerra, L. Wulff, Daniel Barros Jr.:
Optimizing HW/SW Codesign towards Reliability for Critical-Application Systems.
52-57
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- Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita:
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification.
58-63
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- Junichi Hirase:
Economical Importance of the Maximum Chip Area.
64-
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Delay Testing
Fault Modeling & Simulation
Software Testing
Current Testing
Test Engineering
Sequential Circuit Testing
Defect Analysis & Fault Diagnosis
Boundary Scan & Interconnect Testing
FPGA Testing
- Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.
266-271
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- Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita:
Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.
272-277
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- Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi:
A Diagnosis Method for Interconnects in SRAM Based FPGAs.
278-282
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- Sying-Jyan Wang, Chao-Neng Huang:
Testing and Diagnosis of Interconnect Structures in FPGAs.
283-
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On-Line Testing & Fault Tolerance
IDDQ Testing
Memory Testing
Analog & Mixed Signal Test
- Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang:
Dynamic Test Set Generation for Analog Circuits and Systems.
360-365
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- Mike W. T. Wong, Matthew Worsman:
DC Nonlinear Circuit Fault Simulation With Large Change Sensitivity.
366-371
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- Michel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand:
BISTing Switched-Current Circuits.
372-377
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- Y.-T. Chen, C. Su:
Analog Module Metrology Using MNABST-1 P1149.4 Test Chip.
378-382
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- Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.
383-387
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- Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri:
Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis.
388-
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Design Verification
- Chryssa Dislis, Gerry Musgrave, Roger B. Hughes:
Formal Design Techniques - Theory and Engineering Reality.
394-398
Electronic Edition (link) BibTeX
- J. Gong, Eddie M. C. Wong:
Verification of Asynchronous Circuits with Bounded Inertial Gate Delays.
399-401
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- Shing-Wu Tung, Jing-Yang Jou:
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model.
402-407
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- Shin'ichi Nagano, Hiroyuki Fujita, Yoshiaki Kakuda, Tohru Kikuno:
Application of Real-Time Temporal Logic to Design Fault Detection in Responsive Communication Protocols.
408-412
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- Zhen Guo, He Li, Shuling Guo, Dongsheng Wang:
Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer.
413-
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BIST II
- Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault:
A Ring Architecture Strategy for BIST Test Pattern Generation.
418-423
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- Xiaowei Li, Paul Y. S. Cheung:
Exploiting BIST Approach for Two-Pattern Testing.
424-429
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- C. P. Ravikumar, N. Satya Prasad:
Evaluating BIST Architectures for Low Power.
430-434
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- Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A BIST Structure to Test Delay Faults in a Scan Environment.
435-439
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- Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu:
An Examination of PRPG Selection Approaches for Large, Industrial Designs.
440-
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Sequential Circuit Testing
Test Program Generation
Microsystem Testing:
Challenge or Common Knowledge?
Testing Embedded Memories:
Is BIST the Ultimate Solution?
Copyright © Sat May 16 22:59:03 2009
by Michael Ley (ley@uni-trier.de)
