ICCAD 1995:
San Jose,
California,
USA
Richard L. Rudell (Ed.):
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995, San Jose, California, USA, November 5-9, 1995.
IEEE Computer Society 1995, ISBN 0-8186-7213-7 BibTeX
- Robert B. Jones, David L. Dill, Jerry R. Burch:
Efficient validity checking for processor verification.
2-6
Electronic Edition (ACM DL) BibTeX
- Mark Aagaard, Carl-Johan H. Seger:
The formal verification of a pipelined double-precision IEEE floating-point multiplier.
7-10
Electronic Edition (ACM DL) BibTeX
- K. J. Singh, P. A. Subrahmanyam:
Extracting RTL models from transistor netlists.
11-17
Electronic Edition (ACM DL) BibTeX
- Taku Uchino, Fumihiro Minami, Takashi Mitsuhashi, Nobuyuki Goto:
Switching activity analysis using Boolean approximation method.
20-25
Electronic Edition (ACM DL) BibTeX
- Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh:
Estimation and bounding of energy consumption in burst-mode control circuits.
26-33
Electronic Edition (ACM DL) BibTeX
- Tan-Li Chou, Kaushik Roy:
Statistical estimation of sequential circuit activity.
34-37
Electronic Edition (ACM DL) BibTeX
- Mike Chou, Jacob K. White:
Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect.
40-44
Electronic Edition (ACM DL) BibTeX
- Byron Krauter, Lawrence T. Pileggi:
Generating sparse partial inductance matrices with guaranteed stability.
45-52
Electronic Edition (ACM DL) BibTeX
- Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang:
Addressing high frequency effects in VLSI interconnects with full wave model and CFH.
53-56
Electronic Edition (ACM DL) BibTeX
- Shantanu Ganguly, Shervin Hojat:
Clock distribution design and verification for PowerPC microprocessors.
58-61
Electronic Edition (ACM DL) BibTeX
- Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh:
Activity-driven clock design for low power circuits.
62-65
Electronic Edition (ACM DL) BibTeX
- Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay.
66-71
Electronic Edition (ACM DL) BibTeX
- Shipra Panda, Fabio Somenzi:
Who are the variables in your neighborhood.
74-77
Electronic Edition (ACM DL) BibTeX
- Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima:
Efficient construction of binary moment diagrams for verifying arithmetic circuits.
78-82
Electronic Edition (ACM DL) BibTeX
- Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok:
Be careful with don't cares.
83-86
Electronic Edition (ACM DL) BibTeX
- Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich:
Pattern generation for a deterministic BIST scheme.
88-94
Electronic Edition (ACM DL) BibTeX
- Albrecht P. Stroele, Hans-Joachim Wunderlich:
Test register insertion with minimum hardware cost.
95-101
Electronic Edition (ACM DL) BibTeX
- Chen-Yang Pan, Kwang-Ting Cheng:
Pseudo-random testing and signature analysis for mixed-signal circuits.
102-107
Electronic Edition (ACM DL) BibTeX
- Anirudh Devgan:
Efficient and accurate transient simulation in charge-voltage plane.
110-114
Electronic Edition (ACM DL) BibTeX
- D. Zhou, N. Chen, W. Cai:
A fast wavelet collocation method for high-speed VLSI circuit simulation.
115-122
Electronic Edition (ACM DL) BibTeX
- Lars Hedrich, Erich Barke:
A formal approach to nonlinear analog circuit verification.
123-127
Electronic Edition (ACM DL) BibTeX
- Rohini Gupta, Lawrence T. Pileggi:
Constrained multivariable optimization of transmission lines with general topologies.
130-137
Electronic Edition (ACM DL) BibTeX
- John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model.
138-143
Electronic Edition (ACM DL) BibTeX
- Noel Menezes, Ross Baldick, Lawrence T. Pileggi:
A sequential quadratic programming approach to concurrent gate and wire sizing.
144-151
Electronic Edition (ACM DL) BibTeX
- Kavita Ravi, Fabio Somenzi:
High-density reachability analysis.
154-158
Electronic Edition (ACM DL) BibTeX
- Edmund M. Clarke, Masahiro Fujita, Xudong Zhao:
Hybrid decision diagrams.
159-163
Electronic Edition (ACM DL) BibTeX
- Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev:
Synthesizing Petri nets from state-based models.
164-171
Electronic Edition (ACM DL) BibTeX
- Hussain Al-Asaad, John P. Hayes:
Design verification via simulation and automatic test pattern generation.
174-180
Electronic Edition (ACM DL) BibTeX
- Yiming Gong, Sreejit Chakravarty:
On adaptive diagnostic test generation.
181-184
Electronic Edition (ACM DL) BibTeX
- Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee:
Diagnosis of realistic bridging faults with single stuck-at information.
185-192
Electronic Edition (ACM DL) BibTeX
- Nishath K. Verghese, David J. Allstot:
SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits.
194-198
Electronic Edition (ACM DL) BibTeX
- T. Smedes, N. P. van der Meijs, Arjan J. van Genderen:
Extraction of circuit models for substrate cross-talk.
199-206
Electronic Edition (ACM DL) BibTeX
- Kevin J. Kerns, Ivan L. Wemple, Andrew T. Yang:
Stable and efficient reduction of substrate model networks using congruence transforms.
207-214
Electronic Edition (ACM DL) BibTeX
- Hannah Honghua Yang, D. F. Wong:
New algorithms for min-cut replication in partitioned circuits.
216-222
Electronic Edition (ACM DL) BibTeX
- Jianmin Li, John Lillis, Chung-Kuan Cheng:
Linear decomposition algorithm for VLSI design applications.
223-228
Electronic Edition (ACM DL) BibTeX
- Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng:
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm.
229-234
Electronic Edition (ACM DL) BibTeX
- Randal E. Bryant:
Binary decision diagrams and beyond: enabling technologies for formal verification.
236-243
Electronic Edition (ACM DL) BibTeX
- Lawrence T. Pileggi:
Coping with RC(L) interconnect design headaches.
246-253
Electronic Edition (ACM DL) BibTeX
- Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken:
Efficient orthonormality testing for synthesis with pass-transistor selectors.
256-263
Electronic Edition (ACM DL) BibTeX
- Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness:
Logic decomposition during technology mapping.
264-271
Electronic Edition (ACM DL) BibTeX
- Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, S. Prakash:
Efficient use of large don't cares in high-level and logic synthesis.
272-278
Electronic Edition (ACM DL) BibTeX
- Pai H. Chou, Ross B. Ortega, Gaetano Borriello:
Interface co-synthesis techniques for embedded systems.
280-287
Electronic Edition (ACM DL) BibTeX
- Ti-Yen Yen, Wayne Wolf:
Communication synthesis for distributed embedded systems.
288-294
Electronic Edition (ACM DL) BibTeX
- Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi:
Design-for-debugging of application specific designs.
295-301
Electronic Edition (ACM DL) BibTeX
- Manfred Henftling, Hannes C. Wittmann, Kurt Antreich:
A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization.
304-309
Electronic Edition (ACM DL) BibTeX
- Anand Raghunathan, Srimat T. Chakradhar:
Acceleration techniques for dynamic vector compaction.
310-317
Electronic Edition (ACM DL) BibTeX
- Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz:
LOT: logic optimization with testability-new transformations using recursive learning.
318-325
Electronic Edition (ACM DL) BibTeX
- Tanay Karnik, Sung-Mo Kang:
An empirical model for accurate estimation of routing delay in FPGAs.
328-331
Electronic Edition (ACM DL) BibTeX
- Sudip K. Nag, Rob A. Rutenbar:
Performance-driven simultaneous place and route for island-style FPGAs.
332-338
Electronic Edition (ACM DL) BibTeX
- Wai-Kei Mak, D. F. Wong:
Board-level multi-terminal net routing for FPGA-based logic emulation.
339-344
Electronic Edition (ACM DL) BibTeX
- Amit Chowdhary, John P. Hayes:
Technology mapping for field-programmable gate arrays using integer programming.
346-352
Electronic Edition (ACM DL) BibTeX
- Hiroshi Sawada, Takayuki Suyama, Akira Nagoya:
Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization.
353-358
Electronic Edition (ACM DL) BibTeX
- Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
359-363
Electronic Edition (ACM DL) BibTeX
- Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang:
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.
366-370
Electronic Edition (ACM DL) BibTeX
- Hakan Yalcin, John P. Hayes:
Hierarchical timing analysis using conditional delays.
371-377
Electronic Edition (ACM DL) BibTeX
- Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe:
Performance estimation of embedded software with instruction cache modeling.
380-387
Electronic Edition (ACM DL) BibTeX
- Ashok Sudarsanam, Sharad Malik:
Memory bank and register allocation in software synthesis for ASIPs.
388-392
Electronic Edition (ACM DL) BibTeX
- Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang:
Instruction selection using binate covering for code size optimization.
393-399
Electronic Edition (ACM DL) BibTeX
- Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia:
Fast discrete function evaluation using decision diagrams.
402-407
Electronic Edition (ACM DL) BibTeX
- Pranav Ashar, Sharad Malik:
Fast functional simulation using branching programs.
408-412
Electronic Edition (ACM DL) BibTeX
- Scott Woods, Giorgio Casinovi:
Gate-level simulation of digital circuits using multi-valued Boolean algebras.
413-419
Electronic Edition (ACM DL) BibTeX
- Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
An iterative gate sizing approach with accurate delay evaluation.
422-427
Electronic Edition (ACM DL) BibTeX
- R. Iris Bahar, Fabio Somenzi:
Boolean techniques for low power driven re-synthesis.
428-432
Electronic Edition (ACM DL) BibTeX
- Sasan Iman, Massoud Pedram:
Two-level logic minimization for low power.
433-438
Electronic Edition (ACM DL) BibTeX
- Wing Hang Wong, Rajiv Jain:
PARAS: system-level concurrent partitioning and scheduling.
440-445
Electronic Edition (ACM DL) BibTeX
- Miodrag Potkonjak, Wayne Wolf:
Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques.
446-451
Electronic Edition (ACM DL) BibTeX
- Amir H. Farrahi, Majid Sarrafzadeh:
System partitioning to maximize sleep time.
452-455
Electronic Edition (ACM DL) BibTeX
- Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe:
A delay model for logic synthesis of continuously-sized networks.
458-462
Electronic Edition (ACM DL) BibTeX
- Sachin S. Sapatnekar, Weitong Chuang:
Power vs. delay in gate sizing: conflicting objectives?
463-466
Electronic Edition (ACM DL) BibTeX
- Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn:
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.
467-470
Electronic Edition (ACM DL) BibTeX
- Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
Rectangle-packing-based module placement.
472-479
Electronic Edition (ACM DL) BibTeX
- Weiping Shi:
An optimal algorithm for area minimization of slicing floorplans.
480-484
Electronic Edition (ACM DL) BibTeX
- Anmol Mathur, K. C. Chen, C. L. Liu:
Re-engineering of timing constrained placements for regular architectures.
485-490
Electronic Edition (ACM DL) BibTeX
- Farid N. Najm:
Power estimation techniques for integrated circuits.
492-499
Electronic Edition (ACM DL) BibTeX
- Paul E. R. Lippens, Vijay Nagasamy, Wayne Wolf:
CAD challenges in multimedia computing.
502-508
Electronic Edition (ACM DL) BibTeX
- Herman Schmit, Donald E. Thomas:
Address generation for memories containing multiple arrays.
510-514
Electronic Edition (ACM DL) BibTeX
- Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wuytack, Francky Catthoor:
Background memory management for dynamic data structure intensive processing systems.
515-520
Electronic Edition (ACM DL) BibTeX
- Wei Zhao, Christos A. Papachristou:
Architectural partitioning of control memory for application specific programmable processors.
521-526
Electronic Edition (ACM DL) BibTeX
- Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
Cost-free scan: a low-overhead scan path design methodology.
528-533
Electronic Edition (ACM DL) BibTeX
- Sujit Dey, Vijay Gangaram, Miodrag Potkonjak:
A controller-based design-for-testability technique for controller-data path circuits.
534-540
Electronic Edition (ACM DL) BibTeX
- Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On testable multipliers for fixed-width data path architectures.
541-547
Electronic Edition (ACM DL) BibTeX
- Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen:
A high-level design and optimization tool for analog RF receiver front-ends.
550-553
Electronic Edition (ACM DL) BibTeX
- S. R. Kadivar, Doris Schmitt-Landsiedel, H. Klar:
A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters.
554-561
Electronic Edition (ACM DL) BibTeX
- Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
Statistical behavioral modeling and characterization of A/D converters.
562-566
Electronic Edition (ACM DL) BibTeX
- Jason Cong, Lei He:
Optimal wiresizing for interconnects with multiple sources.
568-574
Electronic Edition (ACM DL) BibTeX
- Tianxiong Xue, Ernest S. Kuh:
Post routing performance optimization via multi-link insertion and non-uniform wiresizing.
575-580
Electronic Edition (ACM DL) BibTeX
- Man-Fai Yu, Wayne Wei-Ming Dai:
Single-layer fanout routing and routability analysis for Ball Grid Arrays.
581-586
Electronic Edition (ACM DL) BibTeX
- Nelson L. Passos, Edwin Hsing-Mean Sha:
Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications.
588-591
Electronic Edition (ACM DL) BibTeX
- Fermín Sánchez:
Time-Constrained Loop Pipelining.
592
Electronic Edition (ACM DL) BibTeX
- Anand Raghunathan, Niraj K. Jha:
An iterative improvement algorithm for low power data path synthesis.
597-602
Electronic Edition (ACM DL) BibTeX
- Robert M. Fuhrer, Bill Lin, Steven M. Nowick:
Symbolic hazard-free minimization and encoding of asynchronous finite state machines.
604-611
Electronic Edition (ACM DL) BibTeX
- Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S.
612-617
Electronic Edition (ACM DL) BibTeX
- Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich:
Design based analog testing by Characteristic Observation Inference.
620-626
Electronic Edition (ACM DL) BibTeX
- Giri Devarayanadurg, Mani Soma:
Dynamic test signal design for analog ICs.
627-630
Electronic Edition (ACM DL) BibTeX
- Chauchin Su, Shenshung Chiang, Shyh-Jye Jou:
Impulse response fault model and fault extraction for functional level analog circuit diagnosis.
631-636
Electronic Edition (ACM DL) BibTeX
- Hirendu Vaishnav, Massoud Pedram:
Delay optimal partitioning targeting low power VLSI circuits.
638-643
Electronic Edition (ACM DL) BibTeX
- Roman Kuznar, Franc Brglez:
PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists.
644-649
Electronic Edition (ACM DL) BibTeX
- David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska:
Circuit partitioning with logic perturbation.
650-655
Electronic Edition (ACM DL) BibTeX
- Balakrishnan Iyer, Ramesh Karri, Israel Koren:
Phantom redundancy: a high-level synthesis approach for manufacturability.
658-661
Electronic Edition (ACM DL) BibTeX
- Elof Frank, Thomas Lengauer:
APPlaUSE: Area and performance optimization in a unified placement and synthesis environment.
662-667
Electronic Edition (ACM DL) BibTeX
- Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Synthesis of multiplier-less FIR filters with minimum number of additions.
668-671
Electronic Edition (ACM DL) BibTeX
- Peter Dahlgren:
A multiple-dominance switch-level model for simulation of short faults.
674-680
Electronic Edition (ACM DL) BibTeX
- Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai:
Fault emulation: a new approach to fault grading.
681-686
Electronic Edition (ACM DL) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits.
687-694
Electronic Edition (ACM DL) BibTeX
- Kannan Krishna, Stephen W. Director:
A novel methodology for statistical parameter extraction.
696-699
Electronic Edition (ACM DL) BibTeX
- Boris Troyanovsky, Zhiping Yu, Lydia So, Robert W. Dutton:
Relaxation-based harmonic balance technique for semiconductor device simulation.
700-703
Electronic Edition (ACM DL) BibTeX
- Haifang Liao, Wayne Wei-Ming Dai:
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels.
704-709
Electronic Edition (ACM DL) BibTeX
- Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
A unified approach to topology generation and area optimization of general floorplans.
712-715
Electronic Edition (ACM DL) BibTeX
- Jaewon Kim, Sung-Mo Kang:
A timing-driven data path layout synthesis with integer programming.
716-719
Electronic Edition (ACM DL) BibTeX
- Kai-Yuan Chao, D. F. Wong:
Signal integrity optimization on the pad assignment for high-speed VLSI design.
720-725
Electronic Edition (ACM DL) BibTeX
- Huey-Yih Wang, Robert K. Brayton:
Multi-level logic optimization of FSM networks.
728-735
Electronic Edition (ACM DL) BibTeX
- Krishna P. Belkhale, Alexander J. Suess:
Timing analysis with known false sub graphs.
736-740
Electronic Edition (ACM DL) BibTeX
Copyright © Sat May 16 23:16:29 2009
by Michael Ley (ley@uni-trier.de)
