19. VLSI Design 2006:
Hyderabad,
India
19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India.
IEEE Computer Society 2006, ISBN 0-7695-2502-4 BibTeX
Introduction
Tutorials
- A. V. S. S. Prasad, Jacob Mathews, Nagi Naganathan:
Low-Power Design Strategies for Mobile Computing.
3-4
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- Ruchir Puri, Tanay Karnik, Rajiv V. Joshi:
Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies.
5-7
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- Shiv Tasker, Rishiyur S. Nikhil:
Beyond RTL: Advanced Digital System Design.
8-9
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- Shanthi Pavan, Prakash Easwaran, C. Srinivasan:
System Aspects of Analog to Digital Converter Designs.
10
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- N. S. Nagaraj:
Interconnect Process Variations: Theory and Practice.
11
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- Goutam Debnath, Paul J. Thadikaran:
Design Challenges for High Performance Nano-Technology.
12-13
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- David Abercrombie, Bernd Koenemann, Nagesh Tamarapalli, Srikanth Venkataraman:
DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.
14
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- R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. Krishna Prasad, D. R. Gude:
A Comprehensive SoC Design Methodology for Nanometer Design Challenges.
15-17
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- Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra:
Sequential Equivalence Checking.
18-19
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- Parimal Patel:
Embedded Systems Design Using FPGA.
20
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- Robert C. Lacovara, Dhadesugoor R. Vaman:
Design of Embedded Systems with Novel Applications.
21-22
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Inaugural Keynote Address
Keynotes
Banquet Speeches
Plenary Sessions
Session 1A:
Analog and Mixed-Signal Design I
- K. Narasimhulu, V. Ramgopal Rao:
Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies.
45-50
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- M. S. Bhat, S. Rekha, H. S. Jamadagni:
Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits.
51-56
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- Prabir K. Saha, Ashudeb Dutta, A. Patra, T. K. Bhattacharyya:
Design of a 1 V Low Power 900 MHz QVCO.
57-62
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- Gaurav Raja, Basabi Bhaumik:
16-Bit Segmented Type Current Steering DAC for Video Applications.
63-68
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- Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya:
A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOS.
69-74
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- Koushik De, Santiram Kal:
A Low Power 6-Bit A/D Converter Achieving 10-Bit Resolution for MEMS Sensor Interface Using Time-Interleaved Delta Modulation.
75-80
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Session 1B:
VLSI Technology I
Session 1C:
Interconnect Design I
Session 1D:
Test and Diagnosis
- Tathagato Rai Dastidar, Partha Ray:
A New Device Level Digital Simulator for Simulation and Functional Verification of Large Semiconductor Memories.
155-160
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- Hari Vijay Venkatanarayanan, Michael L. Bushnell:
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip.
161-168
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- Dong Hyun Baik, Kewal K. Saluja:
Test Cost Reduction Using Partitioned Grid Random Access Scan.
169-174
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- Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set.
175-180
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- Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang:
On Methods to Improve Location Based Logic Diagnosis.
181-187
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- Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil:
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.
188-193
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Session 2A:
Communications Module Architecture
Session 2B:
Formal Verification
Session 2C:
VLSI Architecture and FPGAs
Session 2D:
Crosstalk Analysis
- Amit Kumar, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda:
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication.
271-276
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- K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu:
A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff.
277-282
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- Narender Hanchate, Nagarajan Ranganathan:
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.
283-290
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Session 3A:
High-Level and Logic Synthesis
- Samik Das, P. P. Chakrabarti, Pallab Dasgupta:
Instruction-Set-Extension Exploration Using Decomposable Heuristic Search.
293-298
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- Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.
299-304
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- Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik Roychoudhury:
Handling Constraints in Multi-Objective GA for Embedded System Design.
305-310
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- Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu:
A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array.
311-316
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- Rui Zhang, Niraj K. Jha:
State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies.
317-322
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- Jayashree Sridharan, Tom Chen:
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis.
323-328
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Session 3B:
Distribution and Noise Modeling
- R. G. Raghavendra, Pradip Mandal:
An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency.
331-336
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- Puneet Gupta, Andrew B. Kahng:
Efficient Design and Analysis of Robust Power Distribution Meshes.
337-342
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- Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu:
Test Pattern Generation for Power Supply Droop Faults.
343-348
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- Baohua Wang, Pinaki Mazumder:
Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach.
349-354
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- Subodh M. Reddy, Rajeev Murgai:
Accurate Substrate Noise Analysis Based on Library Module Characterization.
355-362
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- Venkat Rao Vallapenani, Ravi Shankar Chevuri, Bingxiong Xu, Lun Ye, Kanad Chakraborty:
Efficient Techniques for Noise Characterization of Sequential Cells and Macros.
363-368
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Session 3C:
Multimedia and Arithmetic Architecture
- Soumyajit Dey, Susmit Biswas, Arijit Mukhopadhyay, Anupam Basu:
An Approach to Architectural Enhancement for Embedded Speech Applications.
371-376
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- Jun Chen, Rong Luo, Huazhong Yang, Hui Wang:
A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator.
377-380
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- Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam:
Performance Optimization with Scalable Reconfigurable Computing Systems.
381-386
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- Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas:
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.
387-392
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- Venkataraman Mahalingam, N. Ranganathan:
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition.
393-398
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- Higinio Mora Mora, Jerónimo Mora Pascual, José-Luis Sánchez Romero, F. Pujol López:
Partial Product Reduction Based on Look-Up Tables.
399-404
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Session 3D:
Test Algorithms
Panel:
VC Forum
Special Session:
Emerging Technologies
Session 4A:
Synthesis and Partitioning
- Ivan Radojevic, Zoran A. Salcic, Partha S. Roop:
Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation.
461-464
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- David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs.
465-468
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- Anirban Lahiri, Saurabh Agarwal, Anupam Basu, Bhargab B. Bhattacharya:
Recovery-Based Real-Time Static Scheduling for Battery Life Optimization.
469-472
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- Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.
473-476
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- Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh:
An Automatic Code Generation Tool for Partitioned Software in Distributed Systems.
477-480
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- Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty:
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm.
481-484
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Session 4B:
Memory and Logic Design
- Motoi Ichihashi, Haruki Toda:
Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation.
487-490
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- Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar:
A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.
491-494
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- Sanjeev K. Jain, Pankaj Agarwal:
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology.
495-498
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- R. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic.
499-502
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- Siva Embanath, Ramakrishnan Venkata:
Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG).
503-506
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- Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti:
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.
507-510
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Session 4C:
Communications and Multimedia Architecture I
- Alok Kumar Pani, Ratnam V. Raja Kumar:
Optimized VLIW Architecture for Non-zero IF QAM-Modem Implementations.
513-516
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- Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti:
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders.
517-520
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- Mian Dong, Chun Zhang, Songping Mai, Zhihua Wang, Dongmei Li:
A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation Microsystems.
521-524
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- Simon Ogg, Bashir M. Al-Hashimi:
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal.
525-529
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- Anand Gautam, A. Geeta Madhuri, Priya Khandelwal, K. Pratyush Aditya, Meghana Desai, Padma N. Krishna, Malvika Dutt, Reeti Bhatia:
Novel Architecture of EBC for JPEG2000.
530-533
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- J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee:
Real Time Dynamic Receive Apodization for an Ultrasound Imaging System.
534-537
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Session 4D:
VLSI Technology II
Session 5A:
Analog and Mixed-Signal Design II
- Zhiyuan Li, Mingyan Yu, Jianguo Ma:
A Rail-to-Rail I/O Operational Amplifier with 0.5% gm Fluctuation Using Double P-channel Differential Input Pairs.
563-568
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- Srikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar:
High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach.
569-574
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- Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran:
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective.
575-580
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- Qadeer Ahmad Khan, G. K. Siddhartha, Divya Tripathi, Sanjay Kumar Wadhwa, Kulbhushan Misri:
Techniques for On-Chip Process Voltage and Temperature Detection and Compensation.
581-586
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- Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee:
Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear Loop.
587-592
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- Sanjoy Kumar Dey, Swapna Banerjee:
An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC.
593-598
Electronic Edition (link) BibTeX
Session 5B:
Low Power/RF Design
- K. Sadeghi, M. Emadi, F. Farbiz:
Using Level Restoring Method for Dual Supply Voltage.
601-605
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- Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak:
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.
606-612
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- Koushik Maharatna, Alfonso Troya, Milos Krstic, Eckhard Grass:
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder.
613-618
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- Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural:
A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC Design.
619-624
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- G. Girishankar, Shitanshu Tiwari:
Generating Scalable Polynomial Models: Key to Low Power High Performance Designs.
625-630
Electronic Edition (link) BibTeX
- Sanjay Kumar Wadhwa, G. K. Siddhartha, Anand Gaurav:
Zero Steady State Current Power on Reset Circuit with Brown-Out Detector.
631-636
Electronic Edition (link) BibTeX
Session 5C:
Embedded Systems
- Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar:
Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems.
639-644
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- Viswanathan Lakshmi Prabha, Elwin Chandra Monie:
Reinforcement Temporal Difference Learning Scheme for Dynamic Energy Management in Embedded Systems.
645-650
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- Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi:
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
651-656
Electronic Edition (link) BibTeX
- Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal:
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
657-664
Electronic Edition (link) BibTeX
Session 5D:
Design Tools
- Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters.
667-671
Electronic Edition (link) BibTeX
- Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin:
Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks.
672-676
Electronic Edition (link) BibTeX
- Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar:
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems.
677-682
Electronic Edition (link) BibTeX
- Sandip Aine, P. P. Chakrabarti, Rajeev Kumar:
Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control.
683-688
Electronic Edition (link) BibTeX
- Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri:
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction.
689-694
Electronic Edition (link) BibTeX
- Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Fast DC Analysis and Its Application to Combinatorial Optimization Problems.
695-700
Electronic Edition (link) BibTeX
Special Session :
Emerging Technologies
- Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler:
Hybrid CMOS/Molecular Electronic Circuits.
703-708
Electronic Edition (link) BibTeX
- Vivek Subramanian, Paul C. Chang, Daniel Huang, Josephine B. Lee, Steven E. Molesa, David R. Redinger, Steven K. Volkman:
All-Printed RFID Tags: Materials, Devices, and Circuit Implications.
709-714
Electronic Edition (link) BibTeX
Session 6A:
Analog Design/MEMS
- Roopak Suri, C. M. Markan:
Threshold Trimming Based Design of a CMOS Programmable Operational Amplifier.
717-720
Electronic Edition (link) BibTeX
- T. K. Bhattacharyya, Shreyas Sen, Debashis Mandal, S. K. Lahiri:
Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor.
721-724
Electronic Edition (link) BibTeX
- Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson:
Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS Vibratory Sensor Electronics.
725-728
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- Soumendu Bhattacharya, Vishwanath Natarajan, Abhijit Chatterjee, Sankar Nair:
Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and Algorithms.
729-733
Electronic Edition (link) BibTeX
- Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan:
Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System.
734-737
Electronic Edition (link) BibTeX
- Supriya S. Shanbhag:
CMOS Integrated Circuit for Sensing Applications.
738-741
Electronic Edition (link) BibTeX
Session 6B:
Low Power Design I
Session 6C:
Interconnect Design II
- Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis:
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.
773-776
Electronic Edition (link) BibTeX
- Alkan Cengiz, Tom Chen:
A Progressive Two-Stage Global Routing for Macro-Cell Based Designs.
777-780
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- Suresh Balasubramanian, Narayanan Natarajan, Olivier Franza, Chris Gianos:
Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains.
781-785
Electronic Edition (link) BibTeX
- Usha Narasimha, Anthony M. Hill, N. S. Nagaraj:
SmartExtract: Accurate Capacitance Extraction for SOC Designs.
786-789
Electronic Edition (link) BibTeX
- Parthasarathi Dasgupta, Prashant Yadava:
Linear Required-Arrival-Time Trees and their Construction.
790-793
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- Snehashis Roy, Sukumar Jairam, H. Udayakumar:
A Methodology for Switching Activity Based IO Powerpad Optimisation.
794-797
Electronic Edition (link) BibTeX
Session 6D:
Test and Design-for-Testability
- Omar I. Khan, Michael L. Bushnell:
Aliasing Analysis of Spectral Statistical Response Compaction Techniques.
801-806
Electronic Edition (link) BibTeX
- Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard:
Testing High-Speed IO Links Using On-Die Circuitry.
807-810
Electronic Edition (link) BibTeX
- Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar:
PIDISC: Pattern Independent Design Independent Seed Compression Technique.
811-817
Electronic Edition (link) BibTeX
- Shweta Chary, Michael L. Bushnell:
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.
818-823
Electronic Edition (link) BibTeX
- Ramesh C. Tekumalla:
An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules.
824-827
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults.
828-831
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Copyright © Sat May 16 23:46:44 2009
by Michael Ley (ley@uni-trier.de)
