VTS 2000:
Montreal,
Canada
18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada.
IEEE Computer Society 2000, ISBN 0-7695-0613-5 BibTeX
Microprocessor Test/Validation
Low Power BIST and Scan
- Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian:
Low Power/Energy BIST Scheme for Datapaths.
23-28
Electronic Edition (link) BibTeX
- Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
Low Power BIST via Non-Linear Hybrid Cellular Automata.
29-34
Electronic Edition (link) BibTeX
- Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba:
Static Compaction Techniques to Control Scan Vector Power Dissipation.
35-42
Electronic Edition (link) BibTeX
Technology Trends and Their Impact on Test
Scan Related Approaches
Defect Driven Techniques
System-on-chip Test Techniques
Analog Test Techniques
BIST:
Arithmetic,
Memories and ILAs
Embedded Tutorial
Temperature and Process Drift Issues
Test Compaction and Design Validation
Analog BIST
Functional Test and Verification Issues
Memory Test
Open Defect Detection,
Diagnosis and Analog BIS
Open Projector
Panel
Delay Test,
Diagnosis and BIST
BIST Issues
STIL Extension,
Jitter,
and Crosstalk
High Level ATPG and Test Scheduling
IDDQ Test
On-line Testing and Fault Tolerance
Panels
Copyright © Sat May 16 23:47:01 2009
by Michael Ley (ley@uni-trier.de)
