ITC 2000:
Atlantic City,
NJ,
USA
Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000.
IEEE Computer Society 2000 BibTeX
@proceedings{DBLP:conf/itc/2000,
title = {Proceedings IEEE International Test Conference 2000, Atlantic
City, NJ, USA, October 2000},
publisher = {IEEE Computer Society},
year = {2000},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 2:
System Test - Lecture Series
Session 3:
Ate Software Generation
Session 4:
Defect Behavior and Analysis Techniques
Session 5:
Industrial Applications
Session 6:
Microprocessor Test
Session 7:
Systems Test
Session 8:
Practical I DDQ Testing For Deep-Submicron Designs
Session 9:
Fault Diagnosis Algorithms And Techniques
Session 10:
Bist Techniques and Applications
Session 11:
Design Validation:
From Function to Timing
- Qiushuang Zhang, Ian G. Harris:
A domain coverage metric for the validation of behavioral VHDL descriptions.
302-308 BibTeX
- Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng:
Static property checking using ATPG vs. BDD techniques.
309-316 BibTeX
- Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits.
317-325 BibTeX
- Nabil M. Abdulrazzaq, Sandeep K. Gupta:
Test generation for path-delay faults in one-dimensional iterative logic arrays.
326-335 BibTeX
Session 12:
Defect- Based Test Mehodologies And The Real World - Lecture Series
Session 13:
Test Techniques For ADCS
Session 14:
Delay Fault Testing
Session 15:
Optimizing Test Effectiveness
Session 16:
Momory Testing
Session 17:
Defect - Based Test Methodologies And The Real World - Lecture Series
Session 18:
From Tester to Applications - Beginning to End
Session 19:
Test For Crosstalk and Bridging Faults
Session 20:
Advances In Test Generation
Session 21:
Embedde Memories Test And Repair
- Kamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor:
Self test architecture for testing complex memory structures.
547-556 BibTeX
- Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni:
A programmable BIST architecture for clusters of multiple-port SRAMs.
557-566 BibTeX
- Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka:
A built-in self-repair analyzer (CRESTA) for embedded DRAMs.
567-574 BibTeX
Session 22:
Board Test
Session 23:
Tester Hardware Issues In Leaping To 1GHZ
Session 24:
Soc Test Solutions
Session 25:
Low-Power Bist
Session 26:
Methodology And Tools For Microprocessor Test
Session 27:
Board Test - lecture Series
Session 28:
Extraction Test And Diagnosis Of Physical Defects
- Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler:
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis.
729-738 BibTeX
- Nilmoni Deb, Ronald D. Blanton:
Analysis of failure sources in surface-micromachined MEMS.
739-749 BibTeX
- Sujit T. Zachariah, Sreejit Chakravarty:
A scalable and efficient methodology to extract two node bridges from large industrial circuits.
750-759 BibTeX
- Charles E. Stroud, John M. Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic:
Bridging fault extraction from physical design data for manufacturing test development.
760-769 BibTeX
Session 29:
Use Models Of IEEE P1500
Session 30:
Quality Bist FOr Logic And FPGA
Session 31:
Detecting All Types Of Faults TS Quickly
Session 32:
FPGA- Lecture Series
Session 33:
Test Techniques for Low-Power Optimization
Session 34:
Test Access Design For Soc'S
- Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian:
HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs.
892-901 BibTeX
- Mehrdad Nourani, Christos A. Papachristou:
An ILP formulation to optimize test access mechanism in system-on-chip testing.
902-910 BibTeX
- Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel:
Wrapper design for embedded core test.
911-920 BibTeX
Session 35:
How Do We Know If Fault Models Areacurate?
Session 36:
High-Frequence Test Techniques
Session 37:
Concurrent Error Detection
Session 38:
The Final Furdle-Signals And Power To the Dut
Session 39:
Mixed-Signal BIST
Session 40:
New Methods For Delay Testing
- Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.
1051-1059 BibTeX
- Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota:
An analysis of the delay defect detection capability of the ECR test method.
1060-1069 BibTeX
- James F. Plusquellic, Amy Germida, Jonathan Hudson, Ernesto Staroswiecki, Chintan Patel:
Predicting device performance from pass/fail transient signal analysis data.
1070-1079 BibTeX
Session 41:
Processor Core Test Techniques
Copyright © Sat May 16 23:26:44 2009
by Michael Ley (ley@uni-trier.de)
