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ITC 2000: Atlantic City, NJ, USA

Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000. IEEE Computer Society 2000 BibTeX
  title     = {Proceedings IEEE International Test Conference 2000, Atlantic
               City, NJ, USA, October 2000},
  publisher = {IEEE Computer Society},
  year      = {2000},
  bibsource = {DBLP, http://dblp.uni-trier.de}

Session 2: System Test - Lecture Series

Session 3: Ate Software Generation

Session 4: Defect Behavior and Analysis Techniques

Session 5: Industrial Applications

Session 6: Microprocessor Test

Session 7: Systems Test

Session 8: Practical I DDQ Testing For Deep-Submicron Designs

Session 9: Fault Diagnosis Algorithms And Techniques

Session 10: Bist Techniques and Applications

Session 11: Design Validation: From Function to Timing

Session 12: Defect- Based Test Mehodologies And The Real World - Lecture Series

Session 13: Test Techniques For ADCS

Session 14: Delay Fault Testing

Session 15: Optimizing Test Effectiveness

Session 16: Momory Testing

Session 17: Defect - Based Test Methodologies And The Real World - Lecture Series

Session 18: From Tester to Applications - Beginning to End

Session 19: Test For Crosstalk and Bridging Faults

Session 20: Advances In Test Generation

Session 21: Embedde Memories Test And Repair

Session 22: Board Test

Session 23: Tester Hardware Issues In Leaping To 1GHZ

Session 24: Soc Test Solutions

Session 25: Low-Power Bist

Session 26: Methodology And Tools For Microprocessor Test

Session 27: Board Test - lecture Series

Session 28: Extraction Test And Diagnosis Of Physical Defects

Session 29: Use Models Of IEEE P1500

Session 30: Quality Bist FOr Logic And FPGA

Session 31: Detecting All Types Of Faults TS Quickly

Session 32: FPGA- Lecture Series

Session 33: Test Techniques for Low-Power Optimization

Session 34: Test Access Design For Soc'S

Session 35: How Do We Know If Fault Models Areacurate?

Session 36: High-Frequence Test Techniques

Session 37: Concurrent Error Detection

Session 38: The Final Furdle-Signals And Power To the Dut

Session 39: Mixed-Signal BIST

Session 40: New Methods For Delay Testing

Session 41: Processor Core Test Techniques

Copyright © Sat May 16 23:26:44 2009 by Michael Ley (ley@uni-trier.de)