ICCD 2003:
San Jose,
CA,
USA
21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings.
IEEE Computer Society 2003, ISBN 0-7695-2025-1 BibTeX
@proceedings{DBLP:conf/iccd/2003,
title = {21st International Conference on Computer Design (ICCD 2003),VLSI
in Computers and Processors, 13-15 October 2003, San Jose, CA,
USA, Proceedings},
booktitle = {ICCD},
publisher = {IEEE Computer Society},
year = {2003},
isbn = {0-7695-2025-1},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynotes
Energy Efficiency
Timing Verification
Electrical Analysis for System LSI
Power Optimization
- Payman Zarkesh-Ha, Ken Doniger, William Loh, Dechang Sun, Rick Stephani, Gordon Priebe:
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors.
84-89
Electronic Edition (link) BibTeX
- Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh:
Precomputation-based Guarding for Dynamic and Leakage Power Reduction.
90-97
Electronic Edition (link) BibTeX
- Saravanan Rajapandian, Zheng Xu, Kenneth L. Shepard:
Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits.
98-102
Electronic Edition (link) BibTeX
- Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy:
Low Power Adder with Adaptive Supply Voltage.
103-106
Electronic Edition (link) BibTeX
- Nestoras Tzartzanis, William W. Walker:
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File.
107-
Electronic Edition (link) BibTeX
Gene Chip Design
Embedded Tutorial
System Level Design
- Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli:
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip.
126-133
Electronic Edition (link) BibTeX
- Vikas Chandra, Gary D. Carpenter, Jeff Burns:
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs.
134-139
Electronic Edition (link) BibTeX
- Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
Interface Synthesis using Memory Mapping for an FPGA Platform.
140-145
Electronic Edition (link) BibTeX
- Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
Efficient Synthesis of Networks On Chip.
146-150
Electronic Edition (link) BibTeX
- Mehrdad Reshadi, Nikil D. Dutt:
Reducing Compilation Time Overhead in Compiled Simulators.
151-
Electronic Edition (link) BibTeX
Systems Performance
Micro Processor Test & Diagnosis
- Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies:
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor.
180-186
Electronic Edition (link) BibTeX
- Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.
187-193
Electronic Edition (link) BibTeX
- Sobeeh Almukhaizim, Thomas Verdel, Yiorgos Makris:
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case.
194-197
Electronic Edition (link) BibTeX
- Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Multiple Fault Diagnosis Using n-Detection Tests.
198-
Electronic Edition (link) BibTeX
Physical Design
- Noriyuki Ito, Hiroaki Komatsu, Yoshiyasu Tanamura, Ryoichi Yamashita, Hiroyuki Sugiyama, Yaroku Sugiyama, Hirofumi Hamamura:
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor.
204-210
Electronic Edition (link) BibTeX
- Yangdong Deng, Wojciech Maly:
Physical Design of the "2.5D" Stacked System.
211-217
Electronic Edition (link) BibTeX
- Bo-Kyung Choi, Huaiyu Xu, Maogang Wang, Majid Sarrafzadeh:
Flow-Based Cell Moving Algorithm for Desired Cell Distribution.
218-
Electronic Edition (link) BibTeX
Performance Optimization
Clock & Signal Distribution
Performance and Power-Driven Physical Design
Instruction Execution
Test Compression Technology
Physical Design for Regular Fabrics and FPGA's
Array Design Optimization
Test Compaction
Techniques for Synthesizing into Fabrics
Hardware Partitioning
Energy-Aware Design and Application
High-Speed Design Issues and Test Challenges
- M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John Poulton:
CMOS High-Speed I/Os - Present and Future.
454-461
Electronic Edition (link) BibTeX
- K. Kiziloglu, S. Seetharaman, K. W. Glass, C. Bil, H. V. Duong, G. Asmanis:
Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors.
462-466
Electronic Edition (link) BibTeX
- Mike P. Li, Jan B. Wilstrup:
Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication Systems.
467-
Electronic Edition (link) BibTeX
Efficiency and Reliability
- Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim, Bumsoo Kim:
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems.
474-480
Electronic Edition (link) BibTeX
- Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Exploiting Microarchitectural Redundancy For Defect Tolerance.
481-488
Electronic Edition (link) BibTeX
- Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron:
Reducing Multimedia Decode Power using Feedback Control.
489-
Electronic Edition (link) BibTeX
Novel Methods in Logic Synthesis
Communications and Context Management
Board Test and Power-Aware Test
Copyright © Sat May 16 23:16:37 2009
by Michael Ley (ley@uni-trier.de)
