Volume 12,
Number 1,
January 2004
- N. Ranganathan:
Editorial.
1-11 BibTeX
- Baris Taskin, Ivan S. Kourtev:
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits.
12-27 BibTeX
- Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang:
Timing modeling and optimization under the transmission line model.
28-41 BibTeX
- Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh:
Timing driven gate duplication.
42-51 BibTeX
- R. Galli, Alexandre F. Tenca:
A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm.
52-66 BibTeX
- Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman:
Substrate coupling in digital circuits in mixed-signal smart-power systems.
67-78 BibTeX
- Antonio H. Chan, Gordon W. Roberts:
A jitter characterization system using a component-invariant Vernier delay line.
79-95 BibTeX
- Tajana Simunic, Stephen P. Boyd, Peter W. Glynn:
Managing power consumption in networks on chips.
96-107 BibTeX
- Girish Varatkar, Radu Marculescu:
On-chip traffic modeling and synthesis for MPEG-2 video applications.
108-119 BibTeX
- Roman L. Lysecky, Susan Cotterell, Frank Vahid:
A fast on-chip profiler memory using a pipelined binary tree.
120-122 BibTeX
Volume 12,
Number 2,
February 2004
- Christian Piguet, Narayanan Vijaykrishnan:
Guest Editorial.
129-130 BibTeX
- Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester:
Statistical analysis of subthreshold leakage current for VLSI circuits.
131-139 BibTeX
- Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
Leakage current reduction in CMOS VLSI circuits by input vector control.
140-154 BibTeX
- Dongwoo Lee, David Blaauw, Dennis Sylvester:
Gate oxide leakage current analysis and reduction for VLSI circuits.
155-166 BibTeX
- Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge:
Circuit and microarchitectural techniques for reducing cache leakage power.
167-184 BibTeX
- Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic:
Level conversion for dual-supply systems.
185-195 BibTeX
- Narender Hanchate, Nagarajan Ranganathan:
LECTOR: a technique for leakage reduction in CMOS circuits.
196-205 BibTeX
- Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao:
The Chimaera reconfigurable functional unit.
206-217 BibTeX
- Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai:
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.
218-226 BibTeX
Volume 12,
Number 3,
March 2004
International Symposium on Low-Power Electronics and Design (ISLPED'02)
- Christian Piguet, Narayanan Vijaykrishnan:
Guest Editorial.
233-234 BibTeX
- Amaury Nève, Helmut Schettler, Thomas Ludwig, Denis Flandre:
Power-delay product minimization in high-performance 64-bit carry-select adders.
235-244 BibTeX
- Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar:
DCG: deterministic clock-gating for low-power microprocessor design.
245-254 BibTeX
- Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii:
Memory energy minimization by data compression: algorithms, architectures and implementation.
255-268 BibTeX
- Edgar G. Daylight, David Atienza, Arnout Vandecappelle, Francky Catthoor, José M. Mendías:
Memory-access-aware data structure transformations for embedded software with dynamic data accesses.
269-280 BibTeX
- Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Ibrahim Kolcu:
Compiler-directed scratch pad memory optimization for embedded multiprocessors.
281-287 BibTeX
- Elias Ahmed, Jonathan Rose:
The effect of LUT and cluster size on deep-submicron FPGA performance and density.
288-298 BibTeX
- Atul Maheshwari, Wayne Burleson, Russell Tessier:
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.
299-311 BibTeX
- Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe:
Overview of a compiler for synthesizing MATLAB programs onto FPGAs.
312-324 BibTeX
- Aristides Efthymiou, Jim D. Garside:
A CAM with mixed serial-parallel comparison for use in low energy caches.
325-329 BibTeX
Volume 12,
Number 4,
April 2004
International Workshop on System Level Interconnect Prediction (SLIP)
- Jeff Alan Davis:
Guest Editorial.
337-338 BibTeX
- Joni Dambre, Dirk Stroobandt, Jan Van Campenhout:
Toward the accurate prediction of placement wire length distributions in VLSI circuits.
339-348 BibTeX
- Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
An electromigration and thermal model of power wires for a priori high-level reliability prediction.
349-358 BibTeX
- Shamik Das, Anantha Chandrakasan, Rafael Reif:
Calibration of Rent's rule models for three-dimensional integrated circuits.
359-366 BibTeX
- James W. Joyner, Payman Zarkesh-Ha, James D. Meindl:
Global interconnect design in a three-dimensional system-on-a-chip.
367-372 BibTeX
- Suhrid A. Wadekar, Alice C. Parker:
Interconnect-based system-level energy and power prediction to guide architecture exploration.
373-380 BibTeX
- PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
On metrics for comparing interconnect estimation methods for FPGAs.
381-385 BibTeX
- Andrey V. Mezhiba, Eby G. Friedman:
Scaling trends of on-chip power distribution noise.
386-394 BibTeX
- Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim:
Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects.
395-407 BibTeX
- Iouliia Skliarova, António de Brito Ferrari:
A software/reconfigurable hardware SAT solver.
408-419 BibTeX
- Khaled Benkrid, Danny Crookes:
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap.
420-436 BibTeX
- Shizhong Mei, Yehea I. Ismail:
Modeling skin and proximity effects with reduced realizable RL circuits.
437-447 BibTeX
Volume 12,
Number 5,
May 2004
Papers
- Pingshan Wang, G. Pei, E. C.-C. Kan:
Pulsed wave interconnect.
453-463 BibTeX
- Himanshu Kaul, Dennis Sylvester:
Low-power on-chip communication based on transition-aware global signaling (TAGS).
464-476 BibTeX
- Peiyi Zhao, Tarek Darwish, Magdy A. Bayoumi:
High-performance and low-power conditional discharge flip-flop.
477-484 BibTeX
- Volkan Kursun, Eby G. Friedman:
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current.
485-496 BibTeX
- Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag:
Reliable low-power digital signal processing via reduced precision redundancy.
497-510 BibTeX
- Nhon T. Quach, Naofumi Takagi, Michael J. Flynn:
Systematic IEEE rounding method for high-speed floating-point multipliers.
511-521 BibTeX
- Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, Keshab K. Parhi:
Design of low-error fixed-width modified booth multiplier.
522-531 BibTeX
Transactions Briefs
Volume 12,
Number 6,
June 2004
- Jennifer L. Wong, Gang Qu, Miodrag Potkonjak:
Power minimization in QoS sensitive systems.
553-561
Electronic Edition (link) BibTeX
- Saraju P. Mohanty, Nagarajan Ranganathan:
A framework for energy and transient power reduction during behavioral synthesis.
562-572
Electronic Edition (link) BibTeX
- Noureddine Chabini, Wayne Wolf:
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.
573-589
Electronic Edition (link) BibTeX
- Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input space adaptive design: a high-level methodology for optimizing energy and performance.
590-602
Electronic Edition (link) BibTeX
- Mahmoud Meribout, Masato Motomura:
Efficient metrics and high-level synthesis for dynamically reconfigurable logic.
603-621
Electronic Edition (link) BibTeX
- Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers:
Pel reconstruction on FPGA-augmented TriMedia.
622-635
Electronic Edition (link) BibTeX
- J. V. Deodhar, Spyros Tragoudas:
Implicit deductive fault simulation for complex delay fault models.
636-641
Electronic Edition (link) BibTeX
- Jun Jin Kong, Keshab K. Parhi:
Low-latency architectures for high-throughput rate Viterbi decoders.
642-651
Electronic Edition (link) BibTeX
- R. Singh, N. Bhat:
An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.
652-657
Electronic Edition (link) BibTeX
- Imed Ben Dhaou, Hannu Tenhunen:
Efficient library characterization for high-level power estimation.
657-661
Electronic Edition (link) BibTeX
- A. Valentian, O. Thomas, Andrei Vladimirescu, Amara Amara:
Modeling subthreshold SOI logic for static timing analysis.
662-669
Electronic Edition (link) BibTeX
Volume 12,
Number 7,
July 2004
- Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha:
Multiple-symbol parallel decoding for variable length codes.
676-685
Electronic Edition (link) BibTeX
- Sumio Morioka, Akashi Satoh:
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
686-691
Electronic Edition (link) BibTeX
- Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu:
Fitted Elmore delay: a simple and accurate interconnect delay model.
691-696
Electronic Edition (link) BibTeX
- Ivan Blunno, Luciano Lavagno:
Designing an asynchronous microcontroller using Pipefitter.
696-699
Electronic Edition (link) BibTeX
- Yongchul Song, Beomsup Kim:
Quadrature direct digital frequency synthesizers using interpolation-based angle rotation.
701-710
Electronic Edition (link) BibTeX
- Jian Liang, Andrew Laffely, S. Srinivasan, Russell Tessier:
An architecture and compiler for scalable on-chip communication.
711-726
Electronic Edition (link) BibTeX
- Arne Halaas, Børge Svingen, Magnar Nedland, Pål Sætrom, Ola R. Snøve Jr., Olaf René Birkeland:
A recursive MISD architecture for pattern matching.
727-734
Electronic Edition (link) BibTeX
- Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho:
Placement constraints in floorplan design.
735-745
Electronic Edition (link) BibTeX
- Yi Zhao, Sujit Dey, Li Chen:
Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.
746-755
Electronic Edition (link) BibTeX
- Sule Ozev, Alex Orailoglu:
Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.
756-765
Electronic Edition (link) BibTeX
- Keoncheol Shin, Taewhan Kim:
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.
766-775
Electronic Edition (link) BibTeX
- Abhijit Jas, Bahram Pouya, Nur A. Touba:
Test data compression technique for embedded cores using virtual scan chains.
775-781
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
780-788
Electronic Edition (link) BibTeX
Volume 12,
Number 8,
August 2004
- Paul Pop, Petru Eles, Zebo Peng, Traian Pop:
Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems.
793-811
Electronic Edition (link) BibTeX
- Peter Petrov, Alex Orailoglu:
Low-power instruction bus encoding for embedded processors.
812-826
Electronic Edition (link) BibTeX
- Yen-Jen Chang, Feipei Lai, Chia-Lin Yang:
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.
827-836
Electronic Edition (link) BibTeX
- Naehyuck Chang, Inseok Choi, Hojun Shim:
DLS: dynamic backlight luminance scaling of liquid crystal display.
837-846
Electronic Edition (link) BibTeX
- Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar:
Asynchronous gate-diffusion-input (GDI) circuits.
847-856
Electronic Edition (link) BibTeX
- Tiberiu Chelcea, Steven M. Nowick:
Robust interfaces for mixed-timing systems.
857-873
Electronic Edition (link) BibTeX
- Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, W. C.-C. Chu:
An orthogonal simulated annealing algorithm for large floorplanning problems.
874-877
Electronic Edition (link) BibTeX
- Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards:
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.
876-880
Electronic Edition (link) BibTeX
Volume 12,
Number 9,
September 2004
- Rouwaida Kanj, Elyse Rosenbaum:
Critical evaluation of SOI design guidelines.
885-894
Electronic Edition (link) BibTeX
- Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Chih-Chen Li, Ron Hu:
A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula.
895-900
Electronic Edition (link) BibTeX
- Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu:
A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.
901-909
Electronic Edition (link) BibTeX
- Li Ding, Pinaki Mazumder:
On circuit techniques to improve noise immunity of CMOS dynamic logic.
910-925
Electronic Edition (link) BibTeX
- Sarvesh H. Kulkarni, Dennis Sylvester:
High performance level conversion for dual VDD design.
926-936
Electronic Edition (link) BibTeX
- Changbo Long, Lei He:
Distributed sleep transistor network for power reduction.
937-946
Electronic Edition (link) BibTeX
- L. T. Clark, M. Morrow, W. Brown:
Reverse-body bias and supply collapse for low effective standby power.
947-956
Electronic Edition (link) BibTeX
- Xinmiao Zhang, Keshab K. Parhi:
High-speed VLSI architectures for the AES algorithm.
957-967
Electronic Edition (link) BibTeX
- J. Kaza, C. Chakrabarti:
Design and implementation of low-energy turbo decoders.
968-977
Electronic Edition (link) BibTeX
- Mathew A. Sacker, Andrew D. Brown, Andrew J. Rushton, Peter R. Wilson:
A behavioral synthesis system for asynchronous circuits.
978-994
Electronic Edition (link) BibTeX
- Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo:
Variable precision arithmetic circuits for FPGA-based multimedia processors.
995-999
Electronic Edition (link) BibTeX
Volume 12,
Number 10,
October 2004
- Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska:
Individual wire-length prediction with application to timing-driven placement.
1004-1014
Electronic Edition (link) BibTeX
- Jason Helge Anderson, Farid N. Najm:
Power estimation techniques for FPGAs.
1015-1027
Electronic Edition (link) BibTeX
- Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction.
1028-1037
Electronic Edition (link) BibTeX
- André DeHon, Raphael Rubin:
Design of FPGA interconnect for multilevel metallization.
1038-1050
Electronic Edition (link) BibTeX
- André DeHon:
Unifying mesh- and tree-based programmable interconnect.
1051-1065
Electronic Edition (link) BibTeX
- Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava:
Empirical models for net-length probability distribution and applications.
1066-1075
Electronic Edition (link) BibTeX
- Ketan N. Patel, Igor L. Markov:
Error-correction and crosstalk avoidance in DSM busses.
1076-1080
Electronic Edition (link) BibTeX
- Payam Heydari, Ravindran Mohanavelu:
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.
1081-1093
Electronic Edition (link) BibTeX
- Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Evaluation of energy consumption in RC ladder circuits driven by a ramp input.
1094-1107
Electronic Edition (link) BibTeX
- Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand:
Assessment of on-chip wire-length distribution models.
1108-1112
Electronic Edition (link) BibTeX
- R. H. Turner, R. F. Woods:
Highly efficient, limited range multipliers for LUT-based FPGA architectures.
1113-1118
Electronic Edition (link) BibTeX
- Stelian Alupoaei, Srinivas Katkoori:
Ant colony system application to macrocell overlap removal.
1118-1123
Electronic Edition (link) BibTeX
- Tali Moreshet, R. Iris Bahar:
Effects of speculation on performance and issue queue design.
1123-1126
Electronic Edition (link) BibTeX
- Mohammad Maymandi-Nejad, Manoj Sachdev:
Correction to "A Digitally Programmable Delay Element: Design and Analysis".
1126-1126
Electronic Edition (link) BibTeX
Volume 12,
Number 11,
November 2004
- Jeong-Taek Kong:
CAD for nanometer silicon design challenges and success.
1132-1147
Electronic Edition (link) BibTeX
- Andrey V. Mezhiba, Eby G. Friedman:
Impedance characteristics of power distribution grids in nanoscale integrated circuits.
1148-1155
Electronic Edition (link) BibTeX
- Alexandre Schmid, Yusuf Leblebici:
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors.
1156-1166
Electronic Edition (link) BibTeX
- Luigi Fortuna, Manuela La Rosa, Donata Nicolosi, Domenico Porto:
Nanoscale system dynamical behaviors: from quantum-dot-based cell to 1-D arrays.
1167-1173
Electronic Edition (link) BibTeX
- E. Y. Chou, J. C. Huang, M. S. Huang, M. C. Hsieh, A. Y. Hsu:
Baud-rate channel equalization in nanometer technologies.
1174-1181
Electronic Edition (link) BibTeX
- J.-L. Lai, P. C.-Y. Wu:
Architectural design and analysis of learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for nanoelectronic systems.
1182-1191
Electronic Edition (link) BibTeX
- Hong-Yi Huang, Shih-Lun Chen:
Interconnect accelerating techniques for sub-100-nm gigascale systems.
1192-1200
Electronic Edition (link) BibTeX
- Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan:
Large-signal two-terminal device model for nanoelectronic circuit analysis.
1201-1208
Electronic Edition (link) BibTeX
- Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang, Qiyu Cai:
Analog-to-digital converter based on single-electron tunneling transistors.
1209-1213
Electronic Edition (link) BibTeX
- C. Dwyer, L. Vicci, J. Poulton, D. Erie, Richard Superfine, Sean Washburn, Russell M. Taylor II:
The design of DNA self-assembled computing circuitry.
1214-1220
Electronic Edition (link) BibTeX
- Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
Characterization and modeling of run-time techniques for leakage power reduction.
1221-1233
Electronic Edition (link) BibTeX
- Kartik Mohanram, Nur A. Touba:
Lowering power consumption in concurrent checkers via input ordering.
1234-1243
Electronic Edition (link) BibTeX
- Ramamurti Chandramouli, Vamsi K. Srikantam:
Multimode power modeling and maximum-likelihood estimation.
1244-1248
Electronic Edition (link) BibTeX
- Antonio Blotti, Roberto Saletti:
Ultralow-power adiabatic circuit semi-custom design.
1248-1253
Electronic Edition (link) BibTeX
- Gerald Esch Jr., Tom Chen:
Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations.
1253-1257
Electronic Edition (link) BibTeX
Volume 12,
Number 12,
December 2004
- Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty:
SOC test planning using virtual test access architectures.
1263-1276
Electronic Edition (link) BibTeX
- Abhijit Jas, C. V. Krishna, Nur A. Touba:
Weighted pseudorandom hybrid BIST.
1277-1283
Electronic Edition (link) BibTeX
- Miron Abramovici, Charles E. Stroud, John M. Emmert:
Online BIST and BIST-based diagnosis of FPGA logic blocks.
1284-1294
Electronic Edition (link) BibTeX
- Magdy A. El-Moursy, Eby G. Friedman:
Power characteristics of inductive interconnect.
1295-1306
Electronic Edition (link) BibTeX
- Emad Gad, Michel S. Nakhla:
Efficient simulation of nonuniform transmission lines using integrated congruence transform.
1307-1320
Electronic Edition (link) BibTeX
- A. Maheshwari, W. Burleson:
Differential current-sensing for on-chip interconnects.
1321-1329
Electronic Edition (link) BibTeX
- Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand:
Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models.
1330-1347
Electronic Edition (link) BibTeX
- Maged Ghoneima, Yehea I. Ismail:
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses.
1348-1359
Electronic Edition (link) BibTeX
- Sanjukta Bhanja, N. Ranganathan:
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs.
1360-1370
Electronic Edition (link) BibTeX
- William N. N. Hung, Xiaoyu Song, T. Kam, Lerong Cheng, Guowu Yang:
Routability checking for three-dimensional architectures.
1371-1374
Electronic Edition (link) BibTeX
- Mauro Olivieri, Francesco Pappalardo, Giuseppe Visalli:
Bus-switch coding for reducing power dissipation in off-chip buses.
1374-1377
Electronic Edition (link) BibTeX
- Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Ron Hu:
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications.
1377-1381
Electronic Edition (link) BibTeX
- Myungchul Yoon:
Sequence-switch coding for low-power data transmission.
1381-1385
Electronic Edition (link) BibTeX
- Irith Pomeranz, Yervant Zorian:
Fault isolation for nonisolated blocks.
1385-1388
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:31:00 2009
by Michael Ley (ley@uni-trier.de)
