Volume 21,
Number 1,
January 2002
- Yih-Chih Chou, Youn-Long Lin:
Effective enforcement of path-delay constraints inperformance-driven placement.
15-22
Electronic Edition (link) BibTeX
- Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje:
An analysis of the wire-load model uncertainty problem.
23-31
Electronic Edition (link) BibTeX
- Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, Henry S. Sheng:
Estimating routing congestion using probabilistic analysis.
32-41
Electronic Edition (link) BibTeX
- Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with hierarchical superconstraints.
42-49
Electronic Edition (link) BibTeX
- Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson:
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters.
50-62
Electronic Edition (link) BibTeX
- Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong:
Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process.
63-71
Electronic Edition (link) BibTeX
- Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh:
Congestion estimation during top-down placement.
72-80
Electronic Edition (link) BibTeX
- Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning.
81-92
Electronic Edition (link) BibTeX
- Sabyasachi Das, Sunil P. Khatri:
An efficient and regular routing methodology for datapath designsusing net regularity extraction.
93-101
Electronic Edition (link) BibTeX
Volume 21,
Number 2,
February 2002
- Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev:
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
109-130
Electronic Edition (link) BibTeX
- Yehea I. Ismail, Eby G. Friedman:
DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect.
131-144
Electronic Edition (link) BibTeX
- Zhaoyun Xing, Russell Kao:
Shortest path search using tiles and piecewise linear costpropagation.
145-158
Electronic Edition (link) BibTeX
- Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw:
Hierarchical analysis of power distribution networks.
159-168
Electronic Edition (link) BibTeX
- Stephen A. Edwards:
An Esterel compiler for large control-dominated systems.
169-183
Electronic Edition (link) BibTeX
- Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Retiming and clock scheduling for digital circuit optimization.
184-203
Electronic Edition (link) BibTeX
- Khurram Muhammad, Kaushik Roy:
A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters.
204-216
Electronic Edition (link) BibTeX
- Said Hamdioui, A. J. van de Goor:
Thorough testing of any multiport memory with linear tests.
217-231
Electronic Edition (link) BibTeX
- Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang:
Domino logic synthesis based on implication graph.
232-240
Electronic Edition (link) BibTeX
- Patrick H. Madden:
Reporting of standard cell placement results.
240-247
Electronic Edition (link) BibTeX
Volume 21,
Number 3,
March 2002
- Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh:
Predicting potential performance for digital circuits.
253-262
Electronic Edition (link) BibTeX
- Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky:
Provably good global buffering by generalized multiterminalmulticommodity flow approximation.
263-274
Electronic Edition (link) BibTeX
- Sung Tae Jung, Chris J. Myers:
Direct synthesis of timed circuits from free-choice STGs.
275-290
Electronic Edition (link) BibTeX
- Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta:
An analysis of system level power management algorithms and theireffects on latency.
291-305
Electronic Edition (link) BibTeX
- Qi Wang, Sarma B. K. Vrudhula:
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits.
306-318
Electronic Edition (link) BibTeX
- Jason Cong, David Zhigang Pan:
Wire width planning for interconnect performance optimization.
319-329
Electronic Edition (link) BibTeX
- Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu:
A fast hierarchical algorithm for three-dimensional capacitanceextraction.
330-336
Electronic Edition (link) BibTeX
- Akio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Ikkei Kinouchi, Yasuaki Inoue:
An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method.
337-348
Electronic Edition (link) BibTeX
- Pramodchandran N. Variyam, Sasikumar Cherubal, Abhijit Chatterjee:
Prediction of analog performance parameters using fast transienttesting.
349-361
Electronic Edition (link) BibTeX
- Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu:
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.
362-368
Electronic Edition (link) BibTeX
Volume 21,
Number 4,
April 2002
- Paolo Crippa, Claudio Turchetti, Massimo Conti:
A statistical methodology for the design of high-performance CMOScurrent-steering digital-to-analog converters.
377-394
Electronic Edition (link) BibTeX
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Circuit simplification for the symbolic analysis of analogintegrated circuits.
395-407
Electronic Edition (link) BibTeX
- Cheng-Ta Hsieh, Massoud Pedram:
Architectural energy optimization by bus splitting.
408-414
Electronic Edition (link) BibTeX
- Nestoras E. Evmorfopoulos, Georgios I. Stamoulis, John N. Avaritsiotis:
A Monte Carlo approach for maximum power estimation based onextreme value theory.
415-432
Electronic Edition (link) BibTeX
- José Luis Rosselló, Jaume Segura:
Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers.
433-448
Electronic Edition (link) BibTeX
- Der-Cheng Huang, Wen-Ben Jone:
A parallel built-in self-diagnostic method for embedded memoryarrays.
449-465
Electronic Edition (link) BibTeX
- Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
On automatic-verification pattern generation for SoC withport-order fault model.
466-479
Electronic Edition (link) BibTeX
- Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu:
Fault simulation and test algorithm generation for random accessmemories.
480-490
Electronic Edition (link) BibTeX
- Wai-Kei Mak:
Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead.
491-497
Electronic Edition (link) BibTeX
- Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay:
Correction to "interconnect synthesis without wire tapering".
497-497
Electronic Edition (link) BibTeX
Volume 21,
Number 5,
May 2002
- Vasco M. Manquinho, João P. Marques Silva:
Search pruning techniques in SAT-based branch-and-bound algorithmsfor the binate covering problem.
505-516
Electronic Edition (link) BibTeX
- Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi:
Efficient synthesis of OTA network for linear analog functions.
517-533
Electronic Edition (link) BibTeX
- Wim Schoenmaker, Peter Meuris:
Electromagnetic interconnects and passives modeling: softwareimplementation issues.
534-543
Electronic Edition (link) BibTeX
- Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu:
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.
544-553
Electronic Edition (link) BibTeX
- Amir H. Salek, Jinan Lou, Massoud Pedram:
Hierarchical buffered routing tree generation.
554-567
Electronic Edition (link) BibTeX
- Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
Fast and exact transistor sizing based on iterative relaxation.
568-581
Electronic Edition (link) BibTeX
- Reinaldo A. Bergamaschi:
Bridging the domains of high-level and logic synthesis.
582-596
Electronic Edition (link) BibTeX
- Anshuman Chandra, Krishnendu Chakrabarty:
Low-power scan testing and test data compression forsystem-on-a-chip.
597-604
Electronic Edition (link) BibTeX
- Emrah Acar, Florentin Dartu, Lawrence T. Pileggi:
TETA: transistor-level waveform evaluation for timing analysis.
605-616
Electronic Edition (link) BibTeX
- Der-Cheng Huang, Wen-Ben Jone:
A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations.
617-628
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.
628-637
Electronic Edition (link) BibTeX
Volume 21,
Number 6,
June 2002
- Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen:
A layout synthesis methodology for array-type analog blocks.
645-661
Electronic Edition (link) BibTeX
- Fei Yuan, Ajoy Opal:
An efficient transient analysis algorithm for mildly nonlinearcircuits.
662-673
Electronic Edition (link) BibTeX
- Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
A new FPGA detailed routing approach via search-based Booleansatisfiability.
674-684
Electronic Edition (link) BibTeX
- Min Ouyang, Michel Toulouse, Krishnaiyan Thulasiraman, Fred Glover, Jitender S. Deogun:
Multilevel cooperative search for the circuit/hypergraphpartitioning problem.
685-693
Electronic Edition (link) BibTeX
- Wanli Jiang, Bapiraju Vinnakota:
Statistical threshold formulation for dynamic Idd test.
694-705
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.
706-714
Electronic Edition (link) BibTeX
- Anshuman Chandra, Krishnendu Chakrabarty:
Test data compression and decompression based on internal scanchains and Golomb coding.
715-722
Electronic Edition (link) BibTeX
- Yungseon Eo, Jongin Shim, William R. Eisenstadt:
A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines.
723-730
Electronic Edition (link) BibTeX
- Antoni Ferré, Joan Figueras:
Leakage power bounds in CMOS digital technologies.
731-738
Electronic Edition (link) BibTeX
- Y. Shin, T. Sakurai:
Power distribution analysis of VLSI interconnects using model orderreduction.
739-745
Electronic Edition (link) BibTeX
Volume 21,
Number 7,
July 2002
- Cesare Alippi:
A probably approximately correct framework to estimate performancedegradation in embedded systems.
749-762
Electronic Edition (link) BibTeX
- Taku Uchino, Jason Cong:
An interconnect energy model considering coupling effects.
763-776
Electronic Edition (link) BibTeX
- Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh:
Pattern routing: use and theory for increasing predictability andavoiding coupling.
777-790
Electronic Edition (link) BibTeX
- Elena Gnani, Vincenzo Giudicissi, Radu Vissarion, Claudio Contiero, Massimo Rudan:
Automatic 2-D and 3-D simulation of parasitic structures insmart-power integrated circuits.
791-798
Electronic Edition (link) BibTeX
- Yu-Shun Guo:
Transient simulation of high-speed interconnects based on thesemidiscretization of Telegrapher's equations.
799-809
Electronic Edition (link) BibTeX
- Priyank Kalla, Maciej J. Ciesielski:
A comprehensive approach to the partial scan problem using implicitstate enumeration.
810-826
Electronic Edition (link) BibTeX
- Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
High-level test compaction techniques.
827-841
Electronic Edition (link) BibTeX
- Seongmoon Wang, Sandeep K. Gupta:
DS-LFSR: a BIST TPG for low switching activity.
842-851
Electronic Edition (link) BibTeX
- Dimitrios Kagaris:
Linear dependencies in extended LFSMs.
852-859
Electronic Edition (link) BibTeX
- Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas:
A new built-in TPG method for circuits with random patternresistant faults.
859-866
Electronic Edition (link) BibTeX
- Congguang Yang, Maciej J. Ciesielski:
BDS: a BDD-based logic optimization system.
866-876
Electronic Edition (link) BibTeX
Volume 21,
Number 8,
August 2002
- Ramesh Karri, Balakrishnan Iyer, Israel Koren:
Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis.
877-888
Electronic Edition (link) BibTeX
- Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana:
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space.
889-903
Electronic Edition (link) BibTeX
- Kaustav Banerjee, Amit Mehrotra:
Analysis of on-chip inductance effects for distributed RLC interconnects.
904-915
Electronic Edition (link) BibTeX
- Steven C. Chan, Kenneth L. Shepard, Dae-Jin Kim:
Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology.
916-927
Electronic Edition (link) BibTeX
- Michael D. Hutton, Jonathan Rose, Derek G. Corneil:
Automatic generation of synthetic sequential benchmark circuits.
928-940
Electronic Edition (link) BibTeX
- Michele Favalli, Marcello Dalpasso:
Bridging fault modeling and simulation for deep submicron CMOS ICs.
941-953
Electronic Edition (link) BibTeX
- Seongmoon Wang, Sandeep K. Gupta:
An automatic test pattern generator for minimizing switching activity during scan testing activity.
954-968
Electronic Edition (link) BibTeX
- Alexandre César Muniz de Oliveira, Luiz Antonio Nogueira Lorena:
A constructive genetic algorithm for gate matrix layout problems.
969-974
Electronic Edition (link) BibTeX
- William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Michael A. Driscoll:
BDD minimization by scatter search.
974-979
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
n-pass n-detection fault simulation and its applications.
980-986
Electronic Edition (link) BibTeX
- Tianhao Zhang, Krishnendu Chakrabarty, Richard B. Fair:
Design of reconfigurable composite microsystems based on hardware/software codesign principles.
987-995
Electronic Edition (link) BibTeX
Volume 21,
Number 9,
September 2002
- Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria:
An instruction-level energy model for embedded VLIW architectures.
998-1010
Electronic Edition (link) BibTeX
- Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices.
1011-1024
Electronic Edition (link) BibTeX
- Jiang Hu, Sachin S. Sapatnekar:
A timing-constrained simultaneous global routing algorithm.
1025-1036
Electronic Edition (link) BibTeX
- Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
High-level energy macromodeling of embedded software.
1037-1050
Electronic Edition (link) BibTeX
- Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli:
Value-sensitive automatic code specialization for embedded software.
1051-1067
Electronic Edition (link) BibTeX
- Irith Pomeranz:
On the use of random limited-scan to improve at-speed randompattern testing of scan circuits.
1068-1076
Electronic Edition (link) BibTeX
- Kaijie Wu, Ramesh Karri:
Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection.
1077-1087
Electronic Edition (link) BibTeX
- Vikram Iyengar, Krishnendu Chakrabarty:
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
1088-1094
Electronic Edition (link) BibTeX
- Dimitrios Kagaris, Spyros Tragoudas:
On the nonenumerative path delay fault simulation problem.
1095-1101
Electronic Edition (link) BibTeX
- Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda:
Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x).
1101-1104
Electronic Edition (link) BibTeX
- Dong Xiang, Hideo Fujiwara:
Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
1105-1113
Electronic Edition (link) BibTeX
Volume 21,
Number 10,
October 2002
- Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Analytical models for crosstalk excitation and propagation in VLSI circuits.
1117-1131
Electronic Edition (link) BibTeX
- Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky:
Area fill synthesis for uniform layout density.
1132-1147
Electronic Edition (link) BibTeX
- Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
A multigrid-like technique for power grid analysis.
1148-1160
Electronic Edition (link) BibTeX
- Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen:
CYCLONE: automated design and layout of RF LC-oscillators.
1161-1170
Electronic Edition (link) BibTeX
- Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty:
Synthesis of single-output space compactors for scan-based sequential circuits.
1171-1179
Electronic Edition (link) BibTeX
- David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran:
Slope propagation in static timing analysis.
1180-1195
Electronic Edition (link) BibTeX
- Gregory Wolfe, Jennifer L. Wong, Miodrag Potkonjak:
Watermarking graph partitioning solutions.
1196-1204
Electronic Edition (link) BibTeX
- Minghorng Lai, Martin D. F. Wong:
Maze routing with buffer insertion and wiresizing.
1205-1209
Electronic Edition (link) BibTeX
- Rung-Bin Lin:
Comments on "Filling algorithms and analyses for layout density control".
1209-1211
Electronic Edition (link) BibTeX
- Srivaths Ravi, Niraj K. Jha:
Test synthesis of systems-on-a-chip.
1211-1217
Electronic Edition (link) BibTeX
- Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Power profile manipulation: a new approach for reducing test application time under power constraints.
1217-1225
Electronic Edition (link) BibTeX
- Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
1225-1232
Electronic Edition (link) BibTeX
Volume 21,
Number 11,
November 2002
- Thanwa Sripramong, Christofer Toumazou:
The invention of CMOS amplifiers using genetic programming and current-flow analysis.
1237-1252
Electronic Edition (link) BibTeX
- Murali Kudlugi, Russell Tessier:
Static scheduling of multidomain circuits for fast functional verification.
1253-1268
Electronic Edition (link) BibTeX
- Hans M. Jacobson, Chris J. Myers:
Efficient algorithms for exact two-level hazard-free logic minimization.
1269-1283
Electronic Edition (link) BibTeX
- Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli:
Dynamic frequency scaling with buffer insertion for mixed workloads.
1284-1305
Electronic Edition (link) BibTeX
- Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto:
Static power modeling of 32-bit microprocessors.
1306-1316
Electronic Edition (link) BibTeX
- Tony Givargis, Frank Vahid:
Platune: a tuning framework for system-on-a-chip platforms.
1317-1327
Electronic Edition (link) BibTeX
- Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu:
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.
1328-1336
Electronic Edition (link) BibTeX
- Ian G. Harris, Russell Tessier:
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures.
1337-1343
Electronic Edition (link) BibTeX
- Yu-Min Lee, Charlie Chung-Ping Chen:
Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method.
1343-1352
Electronic Edition (link) BibTeX
- Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne:
Transition time modeling in deep submicron CMOS.
1352-1363
Electronic Edition (link) BibTeX
- Gang Qu:
Publicly detectable watermarking for intellectual property authentication in VLSI design.
1363-1368
Electronic Edition (link) BibTeX
- Mehmet Can Yildiz, Patrick H. Madden:
Preferred direction Steiner trees.
1368-1372
Electronic Edition (link) BibTeX
Volume 21,
Number 12,
December 2002
- Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai:
Robust Boolean reasoning for equivalence checking and functional property verification.
1377-1394
Electronic Edition (link) BibTeX
- Cagdas Akturan, Margarida F. Jacome:
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors.
1395-1415
Electronic Edition (link) BibTeX
- Tzyy-Kuen Tien, Shih-Chieh Chang, Tong-Kai Tsai:
Crosstalk alleviation for dynamic PLAs.
1416-1424
Electronic Edition (link) BibTeX
- Wim Schoenmaker, Wim Magnus, Peter Meuris, Bert Maleszka:
Renormalization group meshes and the discretization of TCAD equations.
1425-1433
Electronic Edition (link) BibTeX
- Ting-Yuan Wang, Charlie Chung-Ping Chen:
3-D Thermal-ADI: a linear-time chip level transient thermal simulator.
1434-1445
Electronic Edition (link) BibTeX
- Emil Gizdarski, Hideo Fujiwara:
SPIRIT: a highly robust combinational test generation algorithm.
1446-1458
Electronic Edition (link) BibTeX
- Piotr R. Sidorowicz, Janusz A. Brzozowski:
A framework for testing special-purpose memories.
1459-1468
Electronic Edition (link) BibTeX
- Andreas G. Veneris, Magdy S. Abadir:
Design rewiring using ATPG.
1469-1479
Electronic Edition (link) BibTeX
- Maciej J. Ciesielski, Serkan Askar, Samuel Levitin:
Analytical approach to layout generation of datapath cells.
1480-1488
Electronic Edition (link) BibTeX
- Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim:
Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system.
1489-1497
Electronic Edition (link) BibTeX
- Xiaofang Gao, Juin J. Liou, Joe Bernier, Gregg Croft, Adelmo Ortiz-Conde:
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications.
1497-1502
Electronic Edition (link) BibTeX
- Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton:
Test vector generation for charge sharing failures in dynamic logic.
1502-1508
Electronic Edition (link) BibTeX
- Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim:
Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers.
1509-1517
Electronic Edition (link) BibTeX
- Sandeep Koranne:
Formulating SoC test scheduling as a network transportation problem.
1517-1525
Electronic Edition (link) BibTeX
- In-Cheol Park, Hyeong-Ju Kang:
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.
1525-1529
Electronic Edition (link) BibTeX
- Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri:
Design of hierarchical cellular automata for on-chip test pattern generator.
1530-1539
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:23:13 2009
by Michael Ley (ley@uni-trier.de)