9. VLSI Design 1996:
Bangalore,
India
9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India.
IEEE Computer Society 1996 BibTeX
Tutorial Pages
'95 Keynote Address
'96 Keynote Address
Session 1:
Plenary Session:
Invited Address
Session 2:
VLSI for Mobile Communication I
Session 3:
Placement and Routing
Session 4:
Built-In Self-Test and Diagnosis
Session 5:
Hardware/Software Co-Design
Session 6:
Analog Circuits
- A. B. Bhattacharyya, R. S. Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri:
A micropower analog hearing aid on low voltage CMOS digital process.
85-89
Electronic Edition (link) BibTeX
- C. Srinivasan, K. Radhakrishna Rao:
A 20MHz CMOS Variable Gain Amplifier.
90-93
Electronic Edition (link) BibTeX
- Andrea Boni, Carlo Morandi:
Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation.
94-98
Electronic Edition (link) BibTeX
- J. Weiss, B. Majoux, Gérard Bouvier:
A Very High Gain Bandwidth Product Fully Differential Amplifier.
99-102
Electronic Edition (link) BibTeX
Session 7:
Automatic Test Pattern Generation
Session 8:
High-Level Synthesis I
- Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.
122-125
Electronic Edition (link) BibTeX
- Srinivas Katkoori, Ranga Vemuri, Jay Roy:
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis.
126-132
Electronic Edition (link) BibTeX
- Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani:
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS.
133-139
Electronic Edition (link) BibTeX
- Santonu Sarkar, Anupam Basu, Arun K. Majumdar:
Representation and Synthesis of Interface of a Circuit for its Reuse.
140-145
Electronic Edition (link) BibTeX
Session 9:
High-Performance Circuits
Session 10:
Sequential Automatic Test Pattern Generation
Session 12:
High-Level Synthesis II
Session 13:
Field-Programmable Gate Arrays
Session 14:
Mixed-Signal Design and Test
Session 15:
Logic Design and Synthesis
Session 16:
Architecture
Session 17:
Logic and Fault Simulation
Session 18:
VLSI in Communications and Applications
- S. Samel, Bert Gyselinckx, Ivo Bolsens, Hugo De Man:
Designing Systems On Silicon: A Digital Spread Spectrum Pager.
311-312
Electronic Edition (link) BibTeX
- Shriram Kulkarni, Pinaki Mazumder, George I. Haddad:
A high-speed 32-bit parallel correlator for spread spectrum communication.
313-315
Electronic Edition (link) BibTeX
- S. Mitra, S. Das, Parimal Pal Chaudhuri, S. Nandi:
Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins.
316-317
Electronic Edition (link) BibTeX
- Ranjeet Ranade, Sanjay Bhandari, A. N. Chandorkar:
VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder.
318-319
Electronic Edition (link) BibTeX
- Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri:
Cellular automata based architecture of a database query processor.
320-321
Electronic Edition (link) BibTeX
- Jaswinder Pal Singh, A. Kumar, Sanjeev Kumar:
A multiplier generator for Xilinx FPGAs.
322-323
Electronic Edition (link) BibTeX
Session 19:
Low-Power and Analog Design
Session 20:
Test and Logic Synthesis
Session 21:
Low-Power Design
Session 22:
Asynchronous Circuits,
Retiming,
and Paritioning
- Alain Guyot, Marc Renaudin, Bachar El Hassan, Volker Levering:
Self timed division and square-root extraction.
376-381
Electronic Edition (link) BibTeX
- Radhakrishna Nagalla, Graham R. Hellestrand:
Elimination of Dynamic Hazards from Signal Transition Graphs.
382-388
Electronic Edition (link) BibTeX
- Sung-Bum Park, Takashi Nanya:
Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications.
389-392
Electronic Edition (link) BibTeX
- Prathima Agrawal, B. Narendran, Narayanan Shivakumar:
Multi-way partitioning of VLSI circuits.
393-399
Electronic Edition (link) BibTeX
- Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya:
Geometric bipartitioning problem and its applications to VLSI.
400-405
Electronic Edition (link) BibTeX
Session 23:
Delay Testing
Panel Discussion
Copyright © Sat May 16 23:46:42 2009
by Michael Ley (ley@uni-trier.de)