ICCD 1999:
Austin,
Texas,
USA
Proceedings of the IEEE International Conference On Computer Design,
VLSI in Computers and Processors,
ICCD '99,
10-13 October 1999,
Austin,
Texas,
USA. IEEE Computer Society,
1999,
ISBN 0-7695-0406-X
Session 1.1.1:
Keynote Address
Session 1.3.1:
Embedded Tutorial
Session 1.3.2:
Applied Verification Techniques
Session 1.3.3:
Computer Arithmetic
Session 1.4.1:
Machines and Characterization
- Jeff Scott, Lea Hwang Lee, Ann Chin, John Arends, Bill Moyer:
Designing the M·CORETM M3 CPU Architecture.
94-101
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- Mike Clark, Lizy Kurian John:
Performance Evaluation of Configurable Hardware Features on the AMD-K5.
102-107
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- Qiang Cao, Josep Torrellas, Pedro Trancoso, Josep-Lluis Larriba-Pey, Bob Knighten, Youjip Won:
Detailed Characterization of a Quad Pentium Pro Server Running TPC-D.
108-
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Session 1.4.2:
Power and Noise Considerations in Microprocessor Design
Session 1.4.3:
Architectures for Embedded Systems
Session 1.4.4:
Built-In Self Test
Session 1.5.1:
Intelligent Memory
- Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim:
Design and Evaluation of a Selective Compressed Memory System.
184-191
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- Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik:
FlexRAM: Toward an Advanced Intelligent Memory System.
192-201
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- Mark Oskin, Frederic T. Chong, Timothy Sherwood:
ActiveOS: Virtualizing Intelligent Memory.
202-
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Session 1.5.2:
Performance and Area Optimization
Session 1.5.3:
VLSI Implementation of Arithmetic Circuits
Session 1.5.4:
Design Convergence
Session 1.6:
Poster Presentations
- Hasan Cam, Mostafa H. Abd-El-Barr, Sadiq M. Sait:
A High-Performance Hardware-Efficient Memory Allocation Technique and Design.
274-276
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- Rolf Hakenes, Yiannos Manoli:
Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter.
277-278
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- Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada:
A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing.
279-280
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- Ramesh Radhakrishnan, Juan Rubio, Lizy Kurian John:
Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels.
281-284
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- Avinash K. Gautam, V. Visvanathan, S. K. Nandy:
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists.
285-288
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- G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim:
Yield Optimization by Design Centering and Worst-Case Distance Analysis.
289-290
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- Tom Thomas, Brian Anthony:
Area, Performance, and Yield Implications of Redundancy in On-Chip Caches.
291-292
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- Walling R. Cyre:
Conceptual Modeling and Simulation.
293-296
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- Peter James Aldworth:
System-on-a-Chip Bus Architecture for Embedded Applications.
297-298
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- Kyoung-Mook Lim, Seh-Woong Jeong, Yong-Chun Kim, Seung-Jae Jeong, Hong-Kyu Kim, Yang-Ho Kim, Bong-Young Chung, Hyung-Lae Roh, H. S. Yang:
CalmRISCTM: A Low Power Microcontroller with Efficient Coprocessor Interface.
299-302
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- Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai:
An Even Wiring Approach to the Ball Grid Array Package Routing.
303-306
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- Per Lindgren, Rolf Drechsler, Bernd Becker:
Synthesis of Pseudo Kronecker Lattice Diagrams.
307-310
Electronic Edition (link) BibTeX
- Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang:
Generic Universal Switch Blocks.
311-314
Electronic Edition (link) BibTeX
- Ronald W. Mehler, M. Ray Mercer:
Multi-Level Logic Minimization through Fault Dictionary Analysis.
315-318
Electronic Edition (link) BibTeX
- Kang Yi, Seong Yong Ohm:
A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping.
319-320
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- Ashok Kumar, Magdy A. Bayoumi:
Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis.
321-324
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- Chien-Nan Jimmy Liu, Jing-Yang Jou:
An Efficient Functional Coverage Test for HDL Descriptions at RTL.
325-327
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- Hyunjin Kim, Jongchul Shin, Sungho Kang:
An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment.
328-329
Electronic Edition (link) BibTeX
- Jaime Velasco-Medina, Iyad Rayane, Michael Nicolaidis:
On-Line BIST for Testing Analog Circuits.
330-
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Session 2.2.1:
System Level Issues
- Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash G. Chandar:
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.
340-347
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- Sari L. Coumeri, Donald E. Thomas:
An Environment for Exploring Low Power Memory Configurations in System Level Design.
348-353
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- Brandon M. Bachman, Hao Zheng, Chris J. Myers:
Architectural Synthesis of Timed Asynchronous Systems.
354-363
Electronic Edition (link) BibTeX
- Hen-Ming Lin, Jing-Yang Jou:
Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD.
364-
Electronic Edition (link) BibTeX
Session 2.2.2:
Compilers and Algorithms
Session 2.2.3:
Test Generation and Delay Testing
Session 2.3.1:
Microarchitecture
Session 2.3.2:
Efficient State-Space Exploration
Session 2.3.3:
Clocking and Analog Circuit Prototyping
Session 2.3.4:
Embedded Tutorial
Invited Session 2.4.1:
Digital Signal Processors
Session 2.4.2:
Caching Approaches
Session 2.4.3:
CMOS Circuit Design Techniques
Session 3.1:
Plenary
Invited Session 3.2.1
- A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans:
TriMedia CPU64 Application Domain and Benchmark Suite.
580-585
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- Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel:
TriMedia CPU64 Architecture.
586-592
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- Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndhoven, P. Struik, Pieter van der Wolf, Frans Sijstermans, M. J. A. Tromp, Jan-Willem van de Waerdt:
TriMedia CPU64 Application Development Environment.
593-598
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- Gerben J. Hekstra, G. D. La Hei, Peter Bingley, Frans Sijstermans:
TriMedia CPU64 Design Space Exploration.
599-
Electronic Edition (link) BibTeX
Session 3.2.2:
Logic Synthesis
- Imtiaz Ahmad, Raza Ul-Mustafa:
On State Assignment of Finite State Machines Using Hypercube Embedding Approach.
608-613
Electronic Edition (link) BibTeX
- Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi:
Synthesis of Arrays and Records.
614-619
Electronic Edition (link) BibTeX
- Rupesh S. Shelar, Madhav P. Desai, H. Narayanan:
Decomposition of Finite State Machines for Area, Delay Minimization.
620-625
Electronic Edition (link) BibTeX
- Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal:
BDD Decomposition for Efficient Logic Synthesis.
626-
Electronic Edition (link) BibTeX
Session 3.2.3:
Hardware Software Partitioning and Synthesis
Copyright © Sat May 16 23:16:38 2009
by Michael Ley (ley@uni-trier.de)
