ICCAD 1991:
Santa Clara,
California,
USA
IEEE/ACM International Conference on Computer-Aided Design,
ICCAD-91,
November 11-14,
1991,
Santa Clara,
CA,
USA,
Digest of Technical Papers. IEEE Computer Society,
1991,
ISBN 0-8186-2157-5
Physical Partitioning
Analog Simulation
Controller Synthesis
Placement
Interconnect Simulation
Scheduling
Module Generation
Numerical Algorithms
Topics in Logic Synthesis
Real World Framework Applications
Reliability and Manufacturability Analysis
Timing Analysis and Performance Optimization
- Srinivas Devadas, Kurt Keutzer, Sharad Malik:
Delay Computation in Combinational Logic Circuits: Theory and Algorithms.
176-179 BibTeX
- Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions.
180-183 BibTeX
- Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni:
Performance Enhancement through the Generalized Bypass Transform.
184-187 BibTeX
- Hervé J. Touati, Hamid Savoj, Robert K. Brayton:
Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing.
188-191 BibTeX
Diagnostics and Testability Analysis
The False Path Problem in Timing Analysis
Encoding Algorithms
Built-In Self Test
Framework Directions
Techniques for Effective Memory Utilization
- J. Vanhoof, Ivo Bolsens, Hugo De Man:
Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory.
272-275 BibTeX
- Imtiaz Ahmad, C. Y. Roger Chen:
Post-Processor for Data Path Synthesis Using Multiport Memories.
276-279 BibTeX
- Francis Depuydt, Gert Goossens, Hugo De Man:
Clustering Techniques for Register Optimization During Scheduling Preprocessing.
280-283 BibTeX
- Gerben Essink, Emile H. L. Aarts, R. van Dongen, P. van Gerwen, Jan H. M. Korst, Kees A. Vissers:
Scheduling in Programmable Video Signal Processors.
284-287 BibTeX
High-Level Layout Verification
Timing Analysis
Asynchronous Circuit Synthesis
Performance Driven and Parallel Routing Techniques
- Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani:
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers.
332-335 BibTeX
- Ren-Song Tsay:
Exact Zero Skew.
336-339 BibTeX
- Tsukasa Yamauchi, Akio Ishizuka, Toshiyuki Nakata, Nobuyuki Nishiguchi, Nobuhiko Koike:
PROTON: A Parallel Detailed Router on an MIMD Parallel Machine.
340-343 BibTeX
- Rajeev Jayaraman, Rob A. Rutenbar:
A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations.
344-347 BibTeX
Topics in Simulation
Sequential Synthesis and Verification
Analog Circuit and Layout Synthesis
Scan Design
High-Level Synthesis - FSM Synthesis
Detailed Routing
Automatic Test Pattern Generation
Verification Algorithms
- Seh-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi:
Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms.
464-467 BibTeX
- Jawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham:
Probabilistic Design Verification.
468-471 BibTeX
- Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima:
Minimazation of Binary Decision Diagrams Based on Exchanges of Variables.
472-475 BibTeX
- Seon-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi:
Variable Ordering and Selection for FSM Traversal.
476-479 BibTeX
Transistor-Level Optimization and Layout
Design for Testability
Advances in Combinational Synthesis
Exact Algorithms in General Cell Routing
Fault Simulation
Synthesis for FPGA's
Copyright © Sat May 16 23:16:30 2009
by Michael Ley (ley@uni-trier.de)
