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Vinay Dabholkar

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1998
4EEVinay Dabholkar, Sreejit Chakravarty: Computing Stress Tests for Gate Oxide Shorts. VLSI Design 1998: 378-391
3EEVinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy: Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1325-1333 (1998)
1997
2EEVinay Dabholkar, Sreejit Chakravarty: Computing stress tests for interconnect defects. Asian Test Symposium 1997: 143-148
1995
1EEVinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel: Cyclic stress tests for full scan circuits. VTS 1995: 89-94

Coauthor Index

1Sreejit Chakravarty [1] [2] [3] [4]
2J. Najm [1]
3Janak H. Patel [1]
4Irith Pomeranz [3]
5Sudhakar M. Reddy [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)