VTS 1996:
Princeton,
NJ,
USA
14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA.
IEEE Computer Society 1996 BibTeX
Design for Testability
- Nur A. Touba, Edward J. McCluskey:
Test point insertion based on path tracing.
2-8
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- R. D. (Shawn) Blanton, John P. Hayes:
Design of a fast, easily testable ALU.
9-16
Electronic Edition (link) BibTeX
- Fidel Muradali, Janusz Rajski:
A self-driven test structure for pseudorandom testing of non-scan sequential circuits.
17-25
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- Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Scan insertion criteria for low design impact.
26-31
Electronic Edition (link) BibTeX
- Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Segment delay faults: a new fault model.
32-41
Electronic Edition (link) BibTeX
Testability of Analog Circuits
Synthesis for Testability
IDDQ Testing
On-Line Testing
- Egor S. Sogomonyan, Michael Gössel:
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems.
138-144
Electronic Edition (link) BibTeX
- Cecilia Metra, Michele Favalli, Bruno Riccò:
Embedded two-rail checkers with on-line testing ability.
145-150
Electronic Edition (link) BibTeX
- Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis:
An asynchronous totally self-checking two-rail code error indicator.
151-156
Electronic Edition (link) BibTeX
- Steven S. Gorshe, Bella Bose:
A self-checking ALU design with efficient codes.
157-161
Electronic Edition (link) BibTeX
- Vl. V. Saposhnikov, Alexej Dmitriev, Michael Gössel, V. V. Saposhnikov:
Self-dual parity checking-A new method for on-line testing.
162-168
Electronic Edition (link) BibTeX
- Jean-Luis Dufour:
Safety computations in integrated circuits.
169-173
Electronic Edition (link) BibTeX
Fault Diagnosis and Dictionaries
Panel Session
Sequential Circuit Testing
Multi-Chip Modules and Memory Testing
- T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael:
Faulty chip identification in a multi chip module system.
254-259
Electronic Edition (link) BibTeX
- Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan:
Low-cost diagnosis of defects in MCM substrate interconnections.
260-265
Electronic Edition (link) BibTeX
- Vladimir A. Koval, Dmytro V. Fedasyuk:
The MCM's thermal testing.
266-271
Electronic Edition (link) BibTeX
- A. J. van de Goor, G. N. Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik:
March LR: a test for realistic linked faults.
272-280
Electronic Edition (link) BibTeX
- M. P. Kluth, François Simon, Jean-Yves Le Gall, E. Müller:
Design of a fault tolerant 100 Gbits solid-state mass memory for satellite.
281-287
Electronic Edition (link) BibTeX
Delay Fault Testing
Non-Traditional Testing
Panel Session
- R. L. Campbell, P. Kuekes, David Y. Lepejian, W. Maly, Michael Nicolaidis, Alex Orailoglu:
Can Defect-Tolerant Chips Better Meet the Quality Challenge?
362-363
Electronic Edition (link) BibTeX
- Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner:
Design Validation: Formal Verification vs. Simulation vs. Functional Testing.
364-365
Electronic Edition (link) BibTeX
- Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner:
BIST: Advantages or Limitations?
366-367
Electronic Edition (link) BibTeX
Advances in Built-In Self-Test
Fault Modeling and Defect Coverage
Fault Simulation and Test Generation
Mixed-Signal Test Techniques
Panel Session
- Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma:
Delay Fault Testing: How Robust are Our Models?
502-503
Electronic Edition (link) BibTeX
- J. Braden, K. Brough, J. Evans, Martin P. McHugh, G. Young:
Board-Level BIST.
504-505
Electronic Edition (link) BibTeX
- J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard:
Hardware-Software Co-Design for Test: It's the Last Straw!
506-507
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:47:02 2009
by Michael Ley (ley@uni-trier.de)
