Integration, Volume 26

Volume 26, Number 1-2, December 1998

• Bernd Becker:
  Testing with decision diagrams. 5-20
  Electronic Edition (link) BibTeX
• Irith Pomeranz, Sudhakar M. Reddy:
  Delay fault models for VLSI circuits1. 21-40
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• Yong Chang Kim, Kewal K. Saluja:
  Sequential test generators: past, present and future. 41-54
  Electronic Edition (link) BibTeX
• Hans-Joachim Wunderlich:
  BIST for systems-on-a-chip. 55-78
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• Indradeep Ghosh, Niraj K. Jha:
  High-level test synthesis: a survey. 79-99
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• Michiko Inoue, Hideo Fujiwara:
  An approach to test synthesis from higher level. 101-116
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• Anurag Gupta, Kanad Chakraborty, Pinaki Mazumder:
  FTROM: A Silicon Compiler for Fault-tolerant ROMs. 117-140
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• Vishwani D. Agrawal:
  Design of mixed-signal systems for testability. 141-150
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• Mani Soma:
  Mixed-signal on-chip timing measurements. 151-165
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• Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
  IDDQ testing: state of the art and future trends. 167-196
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• Michael Nicolaidis:
  On-line testing for VLSI: state of the art and trends. 197-209
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• Masahide Nakamura, Tohru Kikuno:
  A new approach in feature interaction testing. 211-223
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