DFT 2005:
Monterey,
CA,
USA
20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA.
IEEE Computer Society 2005, ISBN 0-7695-2464-8 BibTeX
Cover
Introduction
Yield Analysis and Modeling
Scan Design and Test Data Compression
Reconfiguration
Error Correcting Codes and Circuits
Fault Detection and Tolerance for Sensor and Flash Memory
- B. Saillet, Jean Michel Portal, Didier Née:
Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring.
131-139
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- Cory Jung, Mohammad Hadi Izadi, Michelle L. La Haye:
Noise Analysis of Fault Tolerant Active Pixel Sensors.
140-148
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- Glenn H. Chapman, Israel Koren, Zahava Koren, Jozsef Dudas, Cory Jung:
On-Line Identification of Faults in Fault-Tolerant Imagers.
149-157
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- Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali:
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems.
158-168
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Delay Fault Test and Timing Consideration
Defect and Fault Tolerant Design in QCA Circuits
Interconnect Test
Case Studies and Applications
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
FPGA oriented design of parity sharing RS codecs.
259-265
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- Mahdi Fazeli, Reza Farivar, Seyed Ghassem Miremadi:
A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems.
266-274
Electronic Edition (link) BibTeX
- G. Cellere, Alessandro Paccagnella, A. Visconti, M. Bonanomi:
Soft Errors induced by single heavy ions in Floating Gate memory arrays.
275-284
Electronic Edition (link) BibTeX
- Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi:
On the Modeling and Analysis of Jitter in ATE Using Matlab.
285-293
Electronic Edition (link) BibTeX
- Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi:
Data Dependent Jitter (DDJ) Characterization Methodology.
294-304
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Interactive Session
- Mohammad Tehranipoor:
Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.
305-313
Electronic Edition (link) BibTeX
- Erik Schüler, Luigi Carro:
Reliable Digital Circuits Design using Sigma-Delta Modulated Signals.
314-324
Electronic Edition (link) BibTeX
- D. P. Vasudevan, Parag K. Lala:
A Technique for Modular Design of Self-Checking Carry-Select Adder.
325-333
Electronic Edition (link) BibTeX
- Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto:
A model of soft error effects in generic IP processors.
334-342
Electronic Edition (link) BibTeX
- Vladimir Ostrovsky, Ilya Levin:
Implementation of Concurrent Checking Circuits by Independent Sub-circuits.
343-351
Electronic Edition (link) BibTeX
- Daniele Rossi, Martin Omaña, Fabio Toma, Cecilia Metra:
Multiple Transient Faults in Logic: An Issue for Next Generation ICs.
352-360
Electronic Edition (link) BibTeX
- Fang Yu, Chung-Hung Tsai, Yao-Wen Huang, D. T. Lee, Hung-Yau Lin, Sy-Yen Kuo:
Efficient Exact Spare Allocation via Boolean Satisfiability.
361-370
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- Jia Di, Parag K. Lala, D. P. Vasudevan:
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.
371-379
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- Bhushan Vaidya, Mehdi Baradaran Tahoori:
Delay Test Generation with All Reachable Output Propagation and Multiple Excitations.
380-388
Electronic Edition (link) BibTeX
- Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi:
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.
389-397
Electronic Edition (link) BibTeX
- Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz:
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.
398-405
Electronic Edition (link) BibTeX
- Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda:
Should Illinois-Scan Based Architectures be Centralized or Distributed?
406-414
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- Leonard Lee, Sean Wu, Charles H.-P. Wen, Li-C. Wang:
On Generating Tests to Cover Diverse Worst-Case Timing Corners.
415-426
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Approaches for Soft Error
On-line and Concurrent Fault Detection
Fault and Error Tolerant Systems
Test Scheduling and Software-based Test
Testing and Design for Analog Circuits
Copyright © Sat May 16 23:06:36 2009
by Michael Ley (ley@uni-trier.de)
