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DFT 2005: Monterey, CA, USA

20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA. IEEE Computer Society 2005, ISBN 0-7695-2464-8 BibTeX



Yield Analysis and Modeling

Scan Design and Test Data Compression


Error Correcting Codes and Circuits

Fault Detection and Tolerance for Sensor and Flash Memory

Delay Fault Test and Timing Consideration

Defect and Fault Tolerant Design in QCA Circuits

Interconnect Test

Case Studies and Applications

Interactive Session

Approaches for Soft Error

On-line and Concurrent Fault Detection

Fault and Error Tolerant Systems

Test Scheduling and Software-based Test

Testing and Design for Analog Circuits

Copyright © Sat May 16 23:06:36 2009 by Michael Ley (ley@uni-trier.de)