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DFT 2006: Arlington, Virginia, USA

21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA. IEEE Computer Society 2006, ISBN 0-7695-2706-X BibTeX

Invited Talk

Adaptive Design and Gate Level Redundancy

Delay Test

Emerging Technologies

Test Compression

Invited Talk

Defect Tolerance and Error Correction

BIST and Pseudo-Functional Test

Reliability Evaluation and Analysis

Approaches for Soft Errors

Interactive Papers

Diagnosis

Defect and Fault Tolerance in Sensors and NOCs

Test Techniques

Processor Checking and Jitter

Fault Tolerance Designs

Copyright © Sat May 16 23:06:36 2009 by Michael Ley (ley@uni-trier.de)