DFT 2006:
Arlington,
Virginia,
USA
21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA.
IEEE Computer Society 2006, ISBN 0-7695-2706-X BibTeX
Invited Talk
Adaptive Design and Gate Level Redundancy
- Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka:
Adaptive Design for Performance-Optimized Robustness.
3-11
Electronic Edition (link) BibTeX
- Tian Xia, Stephen Wyatt, Rupert Ho:
Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration.
12-19
Electronic Edition (link) BibTeX
- Kristian Granhaug, Snorre Aunet:
Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates.
20-28
Electronic Edition (link) BibTeX
- V. Beiu, W. Ibrahim, Y. A. Alkhawwar, M. H. Sulieman:
Gate Failures Effectively Shape Multiplexing.
29-40
Electronic Edition (link) BibTeX
Delay Test
Emerging Technologies
- Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi:
Testing Reversible 1D Arrays for Molecular QCA.
71-79
Electronic Edition (link) BibTeX
- Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park:
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design.
80-88
Electronic Edition (link) BibTeX
- Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi:
Error Tolerance of DNA Self-Assembly by Monomer Concentration Control.
89-97
Electronic Edition (link) BibTeX
- Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim:
Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects.
98-106
Electronic Edition (link) BibTeX
- Reza M. Rad, Mohammad Tehranipoor:
A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices.
107-118
Electronic Edition (link) BibTeX
Test Compression
- Sverre Wichlund, Frank Berntsen, Einar J. Aas:
Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.
119-127
Electronic Edition (link) BibTeX
- Hamidreza Hashempour, Fabrizio Lombardi:
A Novel Methodology for Functional Test Data Compression.
128-135
Electronic Edition (link) BibTeX
- Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito:
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.
136-144
Electronic Edition (link) BibTeX
- Geewhun Seok, Il-soo Lee, Tony Ambler, B. F. Womack:
An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint.
145-156
Electronic Edition (link) BibTeX
Invited Talk
Defect Tolerance and Error Correction
BIST and Pseudo-Functional Test
Reliability Evaluation and Analysis
Approaches for Soft Errors
- Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto:
Combined software and hardware techniques for the design of reliable IP processors.
265-273
Electronic Edition (link) BibTeX
- Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara:
Low-Cost Hardening of Image Processing Applications Against Soft Errors.
274-279
Electronic Edition (link) BibTeX
- Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante:
Online hardening of programs against SEUs and SETs.
280-290
Electronic Edition (link) BibTeX
Interactive Papers
- Chuen-Song Chen, Jien-Chung Lo, Tian Xia:
Equivalent IDDQ Tests for Systems with Regulated Power Supply.
291-299
Electronic Edition (link) BibTeX
- Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský:
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.
300-308
Electronic Edition (link) BibTeX
- Lei Fang, Michael S. Hsiao:
Bilateral Testing of Nano-scale Fault-tolerant Circuits.
309-317
Electronic Edition (link) BibTeX
- Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas:
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates.
318-326
Electronic Edition (link) BibTeX
- Yoichi Sasaki, Kazuteru Namba, Hideo Ito:
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.
327-335
Electronic Edition (link) BibTeX
- Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects.
336-344
Electronic Edition (link) BibTeX
- Á. Michels, Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro:
SET Fault Tolerant Combinational Circuits Based on Majority Logic.
345-352
Electronic Edition (link) BibTeX
- Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi:
An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm.
353-361
Electronic Edition (link) BibTeX
- Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li:
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy.
362-370
Electronic Edition (link) BibTeX
- Marco Ottavi, Salvatore Pontarelli, A. Leandri, Adelio Salsano:
Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers.
371-379
Electronic Edition (link) BibTeX
- Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter:
Recovery Mechanisms for Dual Core Architectures.
380-388
Electronic Edition (link) BibTeX
- Yasser Sedaghat, Seyed Ghassem Miremadi, Mahdi Fazeli:
A Software-Based Error Detection Technique Using Encoded Signatures.
389-400
Electronic Edition (link) BibTeX
Diagnosis
Defect and Fault Tolerance in Sensors and NOCs
- Jozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapman, Israel Koren, Zahava Koren:
On-Line Mapping of In-Field Defects in Image Sensor Arrays.
439-447
Electronic Edition (link) BibTeX
- Michelle L. La Haye, Cory Jung, David Chen, Glenn H. Chapman, Jozsef Dudas:
Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies.
448-456
Electronic Edition (link) BibTeX
- Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande:
NoC Interconnect Yield Improvement Using Crosspoint Redundancy.
457-465
Electronic Edition (link) BibTeX
- Partha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu:
Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding.
466-476
Electronic Edition (link) BibTeX
Test Techniques
Processor Checking and Jitter
Fault Tolerance Designs
Copyright © Sat May 16 23:06:36 2009
by Michael Ley (ley@uni-trier.de)
