22. VLSI Design 2009:
New Delhi,
India
VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009.
IEEE 2009, ISBN 978-0-7695-3506-7 BibTeX
Invited Talks/Special Sessions
Made For India Forum
Panels
Tutorials
- Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Defect Aware to Power Conscious Tests - The New DFT Landscape.
23-25
Electronic Edition (link) BibTeX
- Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín:
Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits.
26-27
Electronic Edition (link) BibTeX
- Anmol Mathur, Qi Wang:
Power Reduction Techniques and Flows at RTL and System Level.
28-29
Electronic Edition (link) BibTeX
- Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel:
Security and Dependability of Embedded Systems: A Computer Architects' Perspective.
30-32
Electronic Edition (link) BibTeX
- Goutam Debnath, Paul J. Thadikaran:
Design for Manufacturability and Reliability in Nano Era.
33-34
Electronic Edition (link) BibTeX
- Nagendra Krishnapura, Shanthi Pavan:
Negative Feedback System and Circuit Design.
35-36
Electronic Edition (link) BibTeX
- Ajit Pal, Santanu Chattopadhyay:
Synthesis & Testing for Low Power.
37-38
Electronic Edition (link) BibTeX
- Samarjit Chakraborty, Ye Wang:
Power Management for Mobile Multimedia: From Audio to Video & Games.
39-40
Electronic Edition (link) BibTeX
- Saurabh K. Tiwary, Amith Singhee, Vikas Chandra:
Robust Circuit Design: Challenges and Solutions.
41-42
Electronic Edition (link) BibTeX
Low Power Design for Wireless Communication
SoC Verification
Fault Diagnosis
- Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
A Novel Approach for Improving the Quality of Open Fault Diagnosis.
85-90
Electronic Edition (link) BibTeX
- Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
91-96
Electronic Edition (link) BibTeX
- Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi:
Efficient Grouping of Fail Chips for Volume Yield Diagnostics.
97-102
Electronic Edition (link) BibTeX
Analog and Mixed Signal I
Floorplanning and Analog Layout
Network on Chip
- Tameesh Suri, Aneesh Aggarwal:
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration.
145-150
Electronic Edition (link) BibTeX
- Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram:
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips.
151-156
Electronic Edition (link) BibTeX
- Amir-Mohammad Rahmani, I. Kamali, Pejman Lotfi-Kamran, Ali Afzali-Kusha, Saeed Safari:
Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips.
157-162
Electronic Edition (link) BibTeX
- Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur:
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration.
163-168
Electronic Edition (link) BibTeX
Low Power Device Technology
System Synthesis
Test Generation
Advanced Device Modeling
Application-Specific Architectures and Reconfigurable Computing
Invited Talk
Embedded Systems I
- Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
High-Speed On-Chip Event Counters for Embedded Systems.
275-280
Electronic Edition (link) BibTeX
- Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios.
281-286
Electronic Edition (link) BibTeX
- Sang-Kyo Han, SeongHoon Woo, Mun-Ho Jeong, Bum-Jae You:
Improved-Quality Real-Time Stereo Vision Processor.
287-292
Electronic Edition (link) BibTeX
SRAM and Random Number Generation
- Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.
295-300
Electronic Edition (link) BibTeX
- Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy:
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS.
301-306
Electronic Edition (link) BibTeX
- Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan:
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.
307-312
Electronic Edition (link) BibTeX
Secure VLSI Design
Embedded Systems II
Analog and Mixed Signal II
- Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
Systematic Methodology for High-Level Performance Modeling of Analog Systems.
361-366
Electronic Edition (link) BibTeX
- Leburu Manojkumar, Arun Mohan, Nagendra Krishnapura:
A Comparison of Approaches to Carrier Generation for Zigbee Transceivers.
367-372
Electronic Edition (link) BibTeX
- Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar:
A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link.
373-378
Electronic Edition (link) BibTeX
Routing,
Power Optimization
- Kimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
381-386
Electronic Edition (link) BibTeX
- Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta:
A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment.
387-392
Electronic Edition (link) BibTeX
- Kaleem Fatima, Rameshwar Rao:
A New Hardware Routing Accelerator for Multi-Terminal Nets.
393-398
Electronic Edition (link) BibTeX
- Shashank Prasad, Anuj Kumar:
Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel.
399-403
Electronic Edition (link) BibTeX
Low Power Design
Analog and Mixed Signal III
Reliability and Design Space Exploration
BIST,
Error Modeling
Advanced Nanodevice Modeling
Timing Analysis and Optimization
Invited Talk
Processor Design and Scheduling
VLSI Education
Invited Paper-Phase Locked Loops
Invited Paper-Design for Variations
Copyright © Sat May 16 23:46:45 2009
by Michael Ley (ley@uni-trier.de)
