9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA.
IEEE Computer Society 1999, ISBN 0-7695-0104-4 BibTeX
@proceedings{DBLP:conf/glvlsi/1999,
title = {9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999,
Ann Arbor, MI, USA},
booktitle = {Great Lakes Symposium on VLSI},
publisher = {IEEE Computer Society},
year = {1999},
isbn = {0-7695-0104-4},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Testing
- Irith Pomeranz, Sudhakar M. Reddy:
PASTA: Partial Scan to Enhance Test Compaction.
4-7
Electronic Edition (link) BibTeX
- Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
On Applying Set Covering Models to Test Set Compaction.
8-11
Electronic Edition (link) BibTeX
- Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On Test Generation with A Limited Number of Tests.
12-15
Electronic Edition (link) BibTeX
- Spyros Tragoudas, Maria K. Michael:
Functional ATPG for Delay Faults.
16-19
Electronic Edition (link) BibTeX
- Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis:
On Path Delay Fault Testing of Multiplexer - Based Shifters.
20-23
Electronic Edition (link) BibTeX
- Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.
24-
Electronic Edition (link) BibTeX
VLSI Design 1
Delay Modeling
VLSI Design 2
Analog and Digital Testing
- Anna Maria Brosa, Joan Figueras:
On Optimizing Test Strategies for Analog Cells.
92-96
Electronic Edition (link) BibTeX
- Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang:
Novel Design for Testability of a Mixed-Signal VLSI IC.
97-100
Electronic Edition (link) BibTeX
- Ying Wang, Han Ngee Tan:
The Development of Analog SPICE Behavioral Model Based on IBIS Model.
101-
Electronic Edition (link) BibTeX
- Mostafa H. Abd-El-Barr, Yanging Xu, Carl McCrosky:
Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits.
388-
Electronic Edition (link) BibTeX
- Von-Kyoung Kim, Tom Chen, Mick Tegethoff:
Fault Coverage Estimation for Early Stage of VLSI Design.
105-108
Electronic Edition (link) BibTeX
- Bassam Shaer, Sami A. Al-Arian, David L. Landis:
Pseudo-Exhaustive Testing of Sequential Circuits.
109-
Electronic Edition (link) BibTeX
Nanoelectronics 1
- James C. Ellenbogen:
Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus.
392-
Electronic Edition (link) BibTeX
- David B. Janes, R. P. Andres, E. H. Chen, J. Dicke, V. R. Kolagunta, J. Lauterbach, T. Lee, J. Liu, M. R. Melloch, E. L. Peckham, T. Pletcher, R. Reifenberger, H. J. Ueng, B. L. Walsh, J. M. Woodall, C. P. Kubiak, B. Kasibhatla:
Self-Assembly Based Approaches for Metal/Molecule/Semiconductor Nanoelectronic Circuits.
114-117
Electronic Edition (link) BibTeX
- Michael T. Niemier, Peter M. Kogge:
Logic in Wire: Using Quantum Dots to Implement a Microprocessor.
118-121
Electronic Edition (link) BibTeX
- Árpád Csurgay, Craig S. Lent, Wolfgang Porod:
Why is Time-Varying Control Necessary for Signal Processing with Locally-Connected Quantum-Dot Arrays?
122-
Electronic Edition (link) BibTeX
- Stephen Marshall Goodnick, Jonathan P. Bird, David K. Ferry, Allen D. Gunther, Maroun D. Khoury, Michael Kozicki, M. J. Rack, T. J. Thornton, D. Vasileska-Kafedezka:
Transport in Split Gate MOS Quantum Dot Structures.
394-
Electronic Edition (link) BibTeX
- T. P. E. Broekaert, B. Brar, F. Morris, A. C. Seabaugh, G. Frazier:
Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain.
123-
Electronic Edition (link) BibTeX
Synthesis
Nanoelectronics 2
- Masafumi Yamamoto, Hideaki Matsuzaki, Toshihiro Itoh, Takao Waho, T. Akeyoshi, J. Osaka:
Ultrahigh-Speed Circuits Using Resonant Tunneling Devices.
150-153
Electronic Edition (link) BibTeX
- Hideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamoto:
A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs.
154-157
Electronic Edition (link) BibTeX
- Tetsuya Uemura, Pinaki Mazumder:
Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit.
158-161
Electronic Edition (link) BibTeX
- Patrick Fay, Gary H. Bernstein, David H. Chow, J. Schulman, Pinaki Mazumder, W. Williamson, B. K. Gilbert:
Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications.
162-165
Electronic Edition (link) BibTeX
- Daniel Berzon, Terry J. Fountain:
A Memory Design in QCAs using the SQUARES Formalism.
166-
Electronic Edition (link) BibTeX
Design Issues
- Chia-Pin R. Liu, Jacob A. Abraham:
Transistor Level Synthesis for Static CMOS Combinational Circuits.
172-175
Electronic Edition (link) BibTeX
- Carlos Humberto Llanos Quintero, Marius Strum:
SINMEF - A Decomposition Based Synthesis Tool for Large FSMs.
176-179
Electronic Edition (link) BibTeX
- Weiwei Li, Zhongwei Xu, Yan Jin:
An Approach for Testing Safety-Critical Software.
180-183
Electronic Edition (link) BibTeX
- Travis E. Doom, Anthony S. Wojcik, Moon-Jung Chung:
Design Recovery for Incomplete Combinational Logic.
184-187
Electronic Edition (link) BibTeX
- Alberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi:
Regression-Based Macromodeling for Delay Estimation of Behavioral Components.
188-191
Electronic Edition (link) BibTeX
- Stephen A. Blythe, Robert A. Walker:
Efficiently Searching the Optimal Design Space.
192-
Electronic Edition (link) BibTeX
VLSI Circuits 1
Short Papers 1
- H.-Ch. Dahmen, Uwe Gläser, Z. Stamenkovic:
Modell Evaluation Using Genetic Manipulation Techniques.
224-225
Electronic Edition (link) BibTeX
- Khaled M. Elleithy, E. G. Abd-El-Fattah:
A Genetic Algorithm for Register Allocation.
226-227
Electronic Edition (link) BibTeX
- Kanad Chakraborty, Natesan Venkateswaran:
Congestion Mitigation During Placement.
228-229
Electronic Edition (link) BibTeX
- John Karro, James P. Cohoon:
A Spiffy Tool for the Simultaneous Placement and Global Routing for Three-Dimensional Field-Programmable Gate Arrays.
230-231
Electronic Edition (link) BibTeX
- Sae Hwan Kim, Shiu-Kai Chin:
Formal Verification of Tree-Structured Carry-Lookahead Adders.
232-233
Electronic Edition (link) BibTeX
- Samit Chaudhuri, Robert A. Walker:
Bounding Algorithms for Design Space Exploration.
234-235
Electronic Edition (link) BibTeX
- Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour:
Digital Neural Processing Unit for Electronic Nose.
236-237
Electronic Edition (link) BibTeX
- Xiaohui Wang, Wolfgang Porod:
A Low Power Charge-Recycling CMOS Clock Buffer.
238-239
Electronic Edition (link) BibTeX
- Richard F. Hobson, Allan R. Dyck:
A Multiple-Input Single-Phase Clock Flip-Flop Family.
240-241
Electronic Edition (link) BibTeX
- Igor Lemberski:
Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs.
242-243
Electronic Edition (link) BibTeX
- Md. Altaf-Ul-Amin, Zahari Mohamed Darus:
VHDL Design of a Test Processor Based on Mixed-Mode Test Generation.
244-
Electronic Edition (link) BibTeX
Physical Design
MEMS
Verification
VLSI Circuits 2
- Amr N. Hafez, Mohamed I. Elmasry:
A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers.
306-309
Electronic Edition (link) BibTeX
- Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang:
NMOS Energy Recovery Logic.
310-313
Electronic Edition (link) BibTeX
- Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman:
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems.
314-317
Electronic Edition (link) BibTeX
- Lim Chu Aun, S. M. Rezaul Hasan:
An all Digital BiCMOS Phase Lock Loop for VLSI Processors.
318-320
Electronic Edition (link) BibTeX
- José Francisco López, Roberto Sarmiento, Antonio Núñez, Kamran Eshraghian, Stefan Lachowicz, Derek Abbott:
Low Power Techniques for Digital GaAs VLSI.
321-324
Electronic Edition (link) BibTeX
- Amr G. Wassal, M. Anwarul Hasan:
A VLSI Architecture for ATM Algorithm-Agile Encryption.
325-
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Short Papers 2
- Dirk Stroobandt:
On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent's Rule.
330-331
Electronic Edition (link) BibTeX
- Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang:
Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS.
332-333
Electronic Edition (link) BibTeX
- S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin:
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures.
334-335
Electronic Edition (link) BibTeX
- Ihn Kim, Craig S. Steele, Jefferey G. Koller:
A Fully Pipelined, 700MBytes/s DES Encryption Core.
386-
Electronic Edition (link) BibTeX
- Teruhiko Kamigata, Koso Murakami, Makoto Iwata, Hiroaki Terada:
Proposal of Data-Driven Processor Architecture Qv-K1.
336-337
Electronic Edition (link) BibTeX
- Srinivas Katkoori, Ranga Vemuri:
Accurate Resource Estimation Algorithms for Behavioral Synthesis.
338-339
Electronic Edition (link) BibTeX
- Von-Kyoung Kim, Tom Chen:
Assessing Defect Coverage of Memory Testing Algorithms.
340-
Electronic Edition (link) BibTeX
- Jacob Savir:
Memory Chip BIST Architecture.
384-
Electronic Edition (link) BibTeX
- Xiaowei Li, Paul Y. S. Cheung:
Exploiting Test Resource Optimization in Data Path Synthesis for BIST.
342-343
Electronic Edition (link) BibTeX
- Christian Pacha, Peter Glösekötter, Karl Goser, U. Auer, W. Prost, F.-J. Tegude:
Resonant Tunneling Transistors for Threshold Logic Circuit Applications.
344-345
Electronic Edition (link) BibTeX
- David Crawley:
A Multilevel Cache Memory Architecture for Nanoelectronics.
346-
Electronic Edition (link) BibTeX
Low Power
VLSI Circuits 3
Copyright © Sat May 16 23:13:52 2009
by Michael Ley (ley@uni-trier.de)
