32. DAC 1995:
San Francisco,
California,
USA
Proceedings of the 32st Conference on Design Automation,
San Francisco,
California,
USA,
Moscone Center,
June 12-16,
1995. ACM Press,
1995,
ISBN 0-89791-725-1
Design of UltraSPARC
- Marc Tremblay, Guillermo Maturana, Atsushi Inoue, Leslie Kohn:
A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-I.
2-6
Electronic Edition (ACM DL) BibTeX
- Lawrence Yang, David Gao, Jamshid Mostoufi, Raju Joshi, Paul Loewenstein:
System Design Methodology of UltraSPARC-I.
7-12
Electronic Edition (ACM DL) BibTeX
- James Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino Jr., Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong:
UltraSPARC-I Emulation.
13-18
Electronic Edition (ACM DL) BibTeX
- A. Cao, A. Adalal, J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan, Manjunath Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin, L. Lev, J. MacDonald, M. Ma, Samir Mitra, P. Patel, A. Prabhu, R. Puranik, S. Rozanski, N. Ross, P. Saggurti, S. Simovich, R. Sunder, B. Sur, W. Vercruysse, Michelle Wong, P. Yip, Robert K. Yu, J. Zhou, Gregory B. Zyner:
CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc.
19-22
Electronic Edition (ACM DL) BibTeX
Power Considerations in Synthesis
- Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino:
Computing the Maximum Power Cycles of a Sequential Circuit.
23-28
Electronic Edition (ACM DL) BibTeX
- Jui-Ming Chang, Massoud Pedram:
Register Allocation and Binding for Low Power.
29-35
Electronic Edition (ACM DL) BibTeX
- Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh:
Memory Segmentation to Exploit Sleep Mode Operation.
36-41
Electronic Edition (ACM DL) BibTeX
- Raul San Martin, John P. Knight:
Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level.
42-47
Electronic Edition (ACM DL) BibTeX
Technology and Layout Dependent Synthesis
Issues in EDA Frameworks
Panel:
Managing Design Process Change - Lessons Learned
Scheduling and Retiming in Architectural Synthesis
Delay Test and Diagnosis
Discrete-Event Simulation
Panel:
Power Minimization in IC Design
Storage Synthesis and Optimization
Retiming and Sequential ATPG
Partitioning and Placement
Design Case Studies
Panel:
University-Industry Ties:
How Can They Be Improved?
Low Power Design
Extraction and Module Generation
Advanced Methods in Practice
- Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, Gil Shurek:
Test Program Generation for Functional Verification of PowerPC Processors in IBM.
279-285
Electronic Edition (ACM DL) BibTeX
- David Knapp, Tai Ly, Don MacMillen, Ron Miller:
Behavioral Synthesis Methodology for HDL-Based Specification and Validation.
286-291
Electronic Edition (ACM DL) BibTeX
- Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza:
Design-Flow and Synthesis for ASICs: A Case Study.
292-297
Electronic Edition (ACM DL) BibTeX
- Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl:
Model Checking in Industrial Hardware Design.
298-303
Electronic Edition (ACM DL) BibTeX
Sequential Logic Synthesis
Fault Modeling and Simulation
CAD for Interconnect
- Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi:
Transmission Line Synthesis.
358-363
Electronic Edition (ACM DL) BibTeX
- Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi:
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals.
364-369
Electronic Edition (ACM DL) BibTeX
- Vasant B. Rao:
Delay Analysis of the Distributed RC Line.
370-375
Electronic Edition (ACM DL) BibTeX
- Luis Miguel Silveira, Mattan Kamon, Jacob White:
Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures.
376-380
Electronic Edition (ACM DL) BibTeX
- Sharad Mehrotra, Paul D. Franzon, Michael Steer:
Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs.
381-387
Electronic Edition (ACM DL) BibTeX
Tutorial:
ASIC Prototyping
Datapath Synthesis and Modeling
Learning and Counterexamples in Formal Verification
Analog CAD
Panel:
DOS,
Windows,
UNIX:
EDA and the O.S. War
Software Analysis and Synthesis
Electrical Simulation
Optimization of Clock and Power Distribution
Concurrent Engineering
- Asim Smailagic, Daniel P. Siewiorek, Drew Anderson, Chris Kasabach, Thomas L. Martin, John Stivoric:
Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems.
514-519
Electronic Edition (ACM DL) BibTeX
- Giovanni Mancini, Dave Yurach, Spiros Boucouris:
A Methodology for HW-SW Codesign in ATM.
520-527
Electronic Edition (ACM DL) BibTeX
- Allan Silburt, Ian Perryman, Janick Bergeron, Stacy Nichols, Mario Dufresne, Greg Ward:
Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation.
528-533
Electronic Edition (ACM DL) BibTeX
Panel:
The ESDA Landscape:
Who Will Dominate?
Formal Verification of Arithmetic Circuits
Routing for FPGAs
EDA and the WWW
Panel:
The Impact of the World Wide Web on Electronic Design and EDA
Code Generation for Embedded Systems
- Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Luciano Lavagno, Harry Hsieh, Kei Suzuki, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich:
Synthesis of Software Programs for Embedded Control Applications.
587-592
Electronic Edition (ACM DL) BibTeX
- Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess:
Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores.
593-598
Electronic Edition (ACM DL) BibTeX
- Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang:
Code Optimization Techniques for Embedded DSP Microprocessors.
599-604
Electronic Edition (ACM DL) BibTeX
- Ulrich Bieker, Peter Marwedel:
Retargetable Self-Test Program Generation Using Constraint Logic Programming.
605-611
Electronic Edition (ACM DL) BibTeX
Switching Activity and Power Analysis
- Farid N. Najm:
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits.
612-617
Electronic Edition (ACM DL) BibTeX
- Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Accurate Estimation of Combinational Circuit Activity.
618-622
Electronic Edition (ACM DL) BibTeX
- Farid N. Najm, Michael Y. Zhang:
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits.
623-627
Electronic Edition (ACM DL) BibTeX
- Radu Marculescu, Diana Marculescu, Massoud Pedram:
Efficient Power Estimation for Highly Correlated Input Streams.
628-634
Electronic Edition (ACM DL) BibTeX
- Farid N. Najm, Shashank Goel, Ibrahim N. Hajj:
Power Estimation in Sequential Circuits.
635-640
Electronic Edition (ACM DL) BibTeX
Combinational Logic Synthesis
- Olivier Coudert, Jean Christophe Madre:
New Ideas for Solving Covering Problems.
641-646
Electronic Edition (ACM DL) BibTeX
- Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
Logic Synthesis for Engineering Change.
647-652
Electronic Edition (ACM DL) BibTeX
- Yuichi Nakamura, Takeshi Yoshimura:
A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix.
653-657
Electronic Edition (ACM DL) BibTeX
- Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita:
Multi-Level Logic Minimization Based on Multi-Signal Implications.
658-662
Electronic Edition (ACM DL) BibTeX
- Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
An Efficient Algorithm for Local Don't Care Sets Calculation.
663-667
Electronic Edition (ACM DL) BibTeX
- Bernhard Rohfleisch, Bernd Wurth, Kurt Antreich:
Logic Clause Analysis for Delay Optimization.
668-672
Electronic Edition (ACM DL) BibTeX
Panel:
Deep Submicron Design Challenges
Complexity Measures for VHDL
Timing Analysis and Optimization
Asynchronous Synthesis
Copyright © Sat May 16 23:04:36 2009
by Michael Ley (ley@uni-trier.de)