11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA.
IEEE Computer Society 2002, ISBN 0-7695-1825-7 BibTeX
@proceedings{DBLP:conf/ats/2002,
title = {11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam,
USA},
booktitle = {Asian Test Symposium},
publisher = {IEEE Computer Society},
year = {2002},
isbn = {0-7695-1825-7},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Test Generation
On-Line Testing
Analog and Mixed Signal Testing
Test Set Compaction
Design for Testability
Memory Testing 1
Delay Fault Testing
Test Synthesis
Memory Testing 2
Crosstalk Fault Testing
Built-in Self Test 1
Fault-Tolerance
Fault Detection and Diagnosis
Built-in Self Test 2
Software Testing
Special Session - Test Strategies and Case Studies for SoC in Industries
- Kazumi Hatayama, Michinobu Nakao, Yasuo Sato:
At-Speed Built-in Test for Logic Circuits with Multiple Clocks.
292-297
Electronic Edition (link) BibTeX
- Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta:
A Test Point Insertion Method to Reduce the Number of Test Patterns.
298-304
Electronic Edition (link) BibTeX
- Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka:
A SoC Test Strategy Based on a Non-Scan DFT Method.
305-310
Electronic Edition (link) BibTeX
- Kazuhiko Iijima, Armagan Akar, Charlie McDonald, Dwayne Burek:
Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips.
311-316
Electronic Edition (link) BibTeX
- Rohit Kapur, Thomas W. Williams:
Manufacturing Test of SoCs.
317-319
Electronic Edition (link) BibTeX
- Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.
320-
Electronic Edition (link) BibTeX
Test Power Reduction
System-on-Chip Testing 1
Verification and Simulation
Test Systems
System-on-Chip Testing 2
- Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng:
Integrated Test Scheduling, Test Parallelization and TAMDesign.
397-404
Electronic Edition (link) BibTeX
- Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng:
Core - Clustering Based SOC Test Scheduling Optimization.
405-410
Electronic Edition (link) BibTeX
- Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
411-
Electronic Edition (link) BibTeX
Current Testing
Copyright © Sat May 16 22:59:04 2009
by Michael Ley (ley@uni-trier.de)
