| |
| 2005 | ||
|---|---|---|
| 2 | EE | Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy: On reducing test application time for scan circuits using limited scan operations and transfer sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1594-1605 (2005) |
| 2004 | ||
| 1 | EE | Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy: Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. ISQED 2004: 211-216 |
| 1 | Irith Pomeranz | [1] [2] |
| 2 | Sudhakar M. Reddy | [1] [2] |