IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 6

Volume 6, Number 1, March 1998

• Pinaki Mazumder:
  Guest Editorial Special Section On Impacts Of Emerging Technologies On VLSI Systems. 4-5
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• Andreas Thiede, Zhi-Gong Wang, Michael Schlechtweg, M. Lang, P. Leber, Zhihao Lao, Ulrich Nowotny, V. Hurm, M. Rieger-Motzer, M. Ludwig, M. Sedler, K. Kohler, W. Bronner, J. Hornung, A. Hulsmann, G. Kaufel, B. Raynor, J. Schneider, T. Jakobus, J. Schroth, Manfred Berroth:
  Mixed signal integrated circuits based on GaAs HEMTs. 6-17
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• Roberto Sarmiento, V. de Armas, José Francisco López, Juan A. Montiel-Nelson, Antonio Núñez:
  A CORDIC processor for FFT computation and its implementation using gallium arsenide technology. 18-30
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• Terry J. Fountain, Michael J. B. Duff, D. G. Crawley, C. D. Tomlinson, C. D. Moffat:
  The use of nanoelectronic devices in highly parallel computing systems. 31-38
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• H. Okazaki, T. Nakagawa, M. Muraguchi, H. Fukuyama, K. Maezawa, Masafumi Yamamoto:
  Sampling phase detector using a resonant tunneling high electron mobility transistor for microwave phase-locked oscillators. 39-42
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• M. Fujii, K. Numata, T. Maeda, M. Tokushima, S. Wada, M. Fukaishi, M. Ishikawa:
  A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's. 43-46
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• Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge:
  Overview of complementary GaAs technology for high-speed VLSI circuits. 47-51
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• Pete M. Campbell, Hans J. Greub, Atul Garg, A. Steidl, Steven R. Carlough, Matthew W. Ernest, Robert F. Philhower, Cliff A. Maier, Russell P. Kraft, John F. McDonald:
  A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's. 52-55
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• Luis A. Plana, Steven M. Nowick:
  Architectural optimization for low-power nonpipelined asynchronous systems. 56-65
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• Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang:
  Statistical estimation of average power dissipation using nonparametric techniques. 65-73
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• Naresh Maheshwari, Sachin S. Sapatnekar:
  Efficient retiming of large circuits. 74-83
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• Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
  SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. 84-100
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• S. K. Jain, Leilei Song, Keshab K. Parhi:
  Efficient semisystolic architectures for finite-field arithmetic. 101-113
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• M. Aberbour, A. Houelle, Habib Mehrez, N. Vaucher, Alain Guyot:
  On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard. 114-121
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• Bapiraju Vinnakota, Jason Andrews:
  Fast fault translation. 122-133
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• Chuan-Yu Wang, Kaushik Roy:
  Maximum power estimation for CMOS circuits using deterministic and statistical approaches. 134-140
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• Stuart F. Oberman, Michael J. Flynn:
  Minimizing the complexity of SRT tables. 141-149
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• L. K. John, E. John:
  A dynamically reconfigurable interconnect for array processors. 150-157
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• Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey:
  Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's. 158-167
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• Arvind Srinivasan, G. D. Huber, David P. LaPotin:
  Accurate area and delay estimation from RTL descriptions. 168-172
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• Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata:
  A novel design of a two operand normalization circuit. 173-176
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• Paul G. Ryan, W. Kent Fuchs:
  Dynamic fault dictionaries and two-stage fault isolation. 176-180
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Volume 6, Number 2, June 1998

• David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow:
  The Transmogrifier-2: a 1 million gate rapid-prototyping system. 188-198
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• Akihiro Tsutsui, Toshiaki Miyazaki:
  ANT-on-YARDS: FPGA/MPU hybrid architecture for telecommunication data processing. 199-211
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• John Lach, William H. Mangione-Smith, Miodrag Potkonjak:
  Low overhead fault-tolerant FPGA systems. 212-221
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• R. Glenn Wood, Rob A. Rutenbar:
  FPGA routing and routability estimation via Boolean satisfiability. 222-231
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• Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses:
  Some experiments about wave pipelining on FPGA's. 232-237
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• Brian Von Herzen:
  Signal processing at 250 MHz using high-performance FPGA's. 238-246
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• Michael J. Wirthlin, Brad L. Hutchings:
  Improving functional density using run-time circuit reconfiguration [FPGAs]. 247-256
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• Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim:
  Fault-tolerant self-organizing map implemented by wafer-scale integration. 257-265
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• William Fornaciari, P. Gubian, Donatella Sciuto, Cristina Silvano:
  Power estimation of embedded systems: a hardware/software codesign approach. 266-275
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• Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi:
  Testing configurable LUT-based FPGA's. 276-283
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• Klaus Herrmann, Jan Otterstedt, H. Jeschke, M. Kuboschek:
  A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm² monolithic implementation. 284-291
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• Luca Breveglieri, Luigi Dadda:
  A VLSI inner product macrocell. 292-298
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• Uming Ko, Poras T. Balsara, Ashwini K. Nanda:
  Energy optimization of multilevel cache architectures for RISC and CISC processors. 299-308
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• Krishnendu Chakrabarty, John P. Hayes:
  Zero-aliasing space compaction of test responses using multiple parity signatures. 309-313
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• Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio:
  Time multiplexed color image processing based on a CNN with cell-state outputs. 314-322
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• S. Bose, P. Agrawal, V. D. Agrawal:
  A rated-clock test method for path delay faults. 323-331
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• S. Bose, P. Agrawal:
  Concurrent fault simulation on message passing multicomputers. 332-342
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Volume 6, Number 3, September 1998

• V. K. Jain, S. Horiguchi:
  VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration. 346-353
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• Christian Legl, Bernd Wurth, Klaus Eckl:
  Computing support-minimal subfunctions during functional decomposition. 354-363
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• Kang-Ngee Chia, Hea Joung Kim, S. Lansing, William H. Mangione-Smith, J. Villasensor:
  High-performance automatic target recognition through data-specific VLSI. 364-371
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• O. Kibar, Philippe J. Marchand, Sadik C. Esener:
  High-speed CMOS switch designs for free-space optoelectronic MIN's. 372-386
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• Daniel Mange, Eduardo Sanchez, André Stauffer, Gianluca Tempesti, Pierre Marchal, Christian Piguet:
  Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties. 387-399
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• Scott Hauck, Gaetano Borriello, Carl Ebeling:
  Mesh routing topologies for multi-FPGA systems. 400-408
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• Karim Arabi, Bozena Kaminska, Mohamad Sawan:
  On chip testing data converters using static parameters. 409-419
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• Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
  Bounds on pseudoexhaustive test lengths. 420-431
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• Irith Pomeranz, Sudhakar M. Reddy:
  On methods to match a test pattern generator to a circuit-under-test. 432-444
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• Vaughn Betz, Jonathan Rose:
  Effect of the prefabricated routing track distribution on FPGA area-efficiency. 445-456
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• Rohini Gupta, John Willis, Lawrence T. Pileggi:
  Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers. 457-463
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• Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu:
  Wave-pipelining: a tutorial and research survey. 464-474
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• Bongjin Jung, Wayne P. Burleson:
  Efficient VLSI for Lempel-Ziv compression in wireless data communication networks. 475-483
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• Zhanping Chen, Kaushik Roy, Tan-Li Chou:
  Efficient statistical approach to estimate power considering uncertain properties of primary inputs. 484-492
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• Marco Winzker:
  Low-power arithmetic for the processing of video signals. 493-497
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• Jianmin Li, Chung-Kuan Cheng:
  Routability improvement using dynamic interconnect architecture. 498-501
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• Franco Fummi, Donatella Sciuto, Cristina Silvano:
  Automatic generation of error control codes for computer applications. 502-506
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• Cesare Alippi, Franco Fummi, Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto:
  Testability analysis and behavioral testing of the Hopfield neural paradigm. 507-511
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Volume 6, Number 4, December 1998

• Anantha Chandrakasan, Edwin Hsing-Mean Sha:
  Special Section on Low-Power Electronics and Design. 518-519
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• Qing Wu, Qinru Qiu, Massoud Pedram, Chih-Shun Ding:
  Cycle-accurate macro-models for RT-level power analysis. 520-528
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• Sven Wuytack, Jean-Philippe Diguet, Francky Catthoor, Hugo De Man:
  Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings. 529-537
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• P. Pant, V. K. De, A. Chatterjee:
  Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits. 538-545
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• Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
  Low-power realization of FIR filters on programmable DSPs. 546-553
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• Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer:
  Power optimization of core-based systems by address bus encoding. 554-562
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• Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry:
  Modeling and comparing CMOS implementations of the C-element. 563-567
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• Enric Musoll, Tomás Lang, Jordi Cortadella:
  Working-zone encoding for reducing the energy in microprocessor address buses. 568-572
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• Dinesh Somasekhar, Kaushik Roy:
  LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. 573-577
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• Alessandro Bogliolo, Luca Benini:
  Robust RTL power macromodels. 578-581
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• K. Ito, Lori E. Lucke, Keshab K. Parhi:
  ILP-based cost-optimal DSP synthesis with module selection and data format conversion. 582-594
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• Tracy C. Denk, Keshab K. Parhi:
  Synthesis of folded pipelined architectures for multirate DSP algorithms. 595-607
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• Sandeep Bhatia, Niraj K. Jha:
  Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. 608-619
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• Jacob Savir:
  Redundancy revisited. 620-624
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• Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim:
  Interleaving buffer insertion and transistor sizing into a single optimization. 625-633
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• Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang:
  On circuit clustering for area/delay tradeoff under capacity and pin constraints. 634-642
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• Kenneth Y. Yun, Peter A. Beerel, Vida Vakilotojar, Ayoob E. Dooply, Julio Arceo:
  The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. 643-655
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• N. R. Shnidman, William H. Mangione-Smith, Miodrag Potkonjak:
  On-line fault detection for bus-based field programmable gate arrays. 656-666
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• Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik:
  Efficient test-point selection for scan-based BIST. 667-676
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• Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man:
  High-level address optimization and synthesis techniques for data-transfer-intensive applications. 677-686
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• Kiyoshi Kobayashi, Shuji Kubota, Kiyoshi Enomoto, K. Seki, K. Kawazoe, Tetsu Sakata, Y. Matsumoto, T. Hattori:
  Low-power and high-quality signal transmission baseband LSIC for personal communications. 687-696
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• Jongwoo Bae, Viktor K. Prasanna:
  Synthesis of area-efficient and high-throughput rate data format converters. 697-706
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• An-Yeu Wu, K. J. Ray Liu:
  Algorithm-based low-power transform coding architectures: the multirate approach. 707-718
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• Nelson L. Passos, Edwin Hsing-Mean Sha:
  Scheduling of uniform multidimensional systems under resource constraints. 719-730
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• Dave Johnson, Venkatesh Akella, Bret Stott:
  Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. 731-740
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