Volume 14,
Number 1,
January 2006
- Yajun Ran, Malgorzata Marek-Sadowska:
Designing via-configurable logic blocks for regular fabric.
1-14
Electronic Edition (link) BibTeX
- Amine Bermak, Yat-Fong Yung:
A DPS array with programmable resolution and reconfigurable conversion time.
15-22
Electronic Edition (link) BibTeX
- Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
SWAN: high-level simulation methodology for digital substrate noise generation.
23-33
Electronic Edition (link) BibTeX
- Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu:
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy.
34-42
Electronic Edition (link) BibTeX
- Y. Eslami, Ali Sheikholeslami, P. Glenn Gulak, S. Masui, K. Mukaida:
An area-efficient universal cryptography processor for smart cards.
43-56
Electronic Edition (link) BibTeX
- Ali Habibi, Sofiène Tahar:
Design and verification of SystemC transaction-level models.
57-68
Electronic Edition (link) BibTeX
- Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel:
Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction.
69-80
Electronic Edition (link) BibTeX
- Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
A power-driven multiplication instruction-set design method for ASIPs.
81-85
Electronic Edition (link) BibTeX
- Yuming Zhu, L. Li, C. Chakrabarti:
Study of energy and performance of space-time decoding systems in concatenation with turbo decoding.
86-90
Electronic Edition (link) BibTeX
- Sagar S. Sabade, D. M. H. Walker:
Estimation of fault-free leakage current using wafer-level spatial information.
91-94
Electronic Edition (link) BibTeX
Volume 14,
Number 2,
February 2006
- Girish N. Patel, Michael S. Reid, David E. Schimmel, Stephen P. DeWeerth:
An asynchronous architecture for modeling intersegmental neural communication.
97-110
Electronic Edition (link) BibTeX
- Orlando J. Hernandez:
A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm.
111-121
Electronic Edition (link) BibTeX
- Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Energy optimization of pipelined digital systems using circuit sizing and supply scaling.
122-134
Electronic Edition (link) BibTeX
- J. Khan, R. Vemuri:
Energy management for battery-powered reconfigurable computing platforms.
135-147
Electronic Edition (link) BibTeX
- Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
Low-power network-on-chip for high-performance SoC design.
148-160
Electronic Edition (link) BibTeX
- Guoqing Chen, Eby G. Friedman:
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.
161-172
Electronic Edition (link) BibTeX
- Lin Yuan, Gang Qu:
A combined gate replacement and input vector control approach for leakage current reduction.
173-182
Electronic Edition (link) BibTeX
- Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET.
183-192
Electronic Edition (link) BibTeX
- Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke:
X-masking during logic BIST and its impact on defect coverage.
193-202
Electronic Edition (link) BibTeX
- Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy:
Layout-driven architecture synthesis for high-speed digital filters.
203-207
Electronic Edition (link) BibTeX
- Pedro Julián, Andreas G. Andreou, David H. Goldberg:
A low-power correlation-derivative CMOS VLSI circuit for bearing estimation.
207-212
Electronic Edition (link) BibTeX
- J. J. Rodriguez-Navarro:
Comments on "Carry checking/parity prediction adders and ALUs".
212-213
Electronic Edition (link) BibTeX
Volume 14,
Number 3,
March 2006
- Mikhail Popovich, Eby G. Friedman:
Decoupling capacitors for multi-voltage power distribution systems.
217-228
Electronic Edition (link) BibTeX
- Woon Kang, Yong-Bin Kim, T. Doyle:
A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine.
229-240
Electronic Edition (link) BibTeX
- Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane:
FABSYN: floorplan-aware bus architecture synthesis.
241-253
Electronic Edition (link) BibTeX
- Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim:
A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth.
254-267
Electronic Edition (link) BibTeX
- Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, T. Balsara:
A nonredundant ternary CAM circuit for network search engines.
268-278
Electronic Edition (link) BibTeX
- Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis:
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.
279-291
Electronic Edition (link) BibTeX
- Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty:
Test infrastructure design for mixed-signal SOCs with wrapped analog cores.
292-304
Electronic Edition (link) BibTeX
- Erik Larsson, Hideo Fujiwara:
System-on-chip test scheduling with reconfigurable core wrappers.
305-309
Electronic Edition (link) BibTeX
Volume 14,
Number 4,
April 2006
- Byung-Do Yang, Lee-Sup Kim:
A low-power ROM using single charge-sharing capacitor and hierarchical bit line.
313-322
Electronic Edition (link) BibTeX
- Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi:
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.
323-335
Electronic Edition (link) BibTeX
- Byonghyo Shim, Naresh R. Shanbhag:
Energy-efficient soft error-tolerant digital signal processing.
336-348
Electronic Edition (link) BibTeX
- Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya:
Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation.
349-360
Electronic Edition (link) BibTeX
- Shih-Chang Hsia, Ming-Huei Chen, Po-Shien Tsai:
VLSI implementation of low-power high-quality color interpolation processor for CCD camera.
361-369
Electronic Edition (link) BibTeX
- Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert:
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers.
370-379
Electronic Edition (link) BibTeX
- Sangjin Hong, Kyoung-Su Park, Jun-Hee Mun:
Design and implementation of a high-speed matrix multiplier based on word-width decomposition.
380-392
Electronic Edition (link) BibTeX
- Kamran Farzan, David A. Johns:
Coding schemes for chip-to-chip interconnect applications.
393-406
Electronic Edition (link) BibTeX
- Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod:
Linear-programming-based techniques for synthesis of network-on-chip architectures.
407-420
Electronic Edition (link) BibTeX
- Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn:
Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing.
421-425
Electronic Edition (link) BibTeX
- Chien-Ching Lin, Y.-H. Shih, Hsie-Chia Chang, Chen-Yi Lee:
A low power turbo/Viterbi decoder for 3GPP2 applications.
426-430
Electronic Edition (link) BibTeX
- Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai:
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs.
430-435
Electronic Edition (link) BibTeX
Volume 14,
Number 5,
May 2006
- Peng Rong, Massoud Pedram:
An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries.
441-451
Electronic Edition (link) BibTeX
- Massimo Alioto, Gaetano Palumbo, Massimo Poli:
Energy Consumption in RC Tree Circuits.
452-461
Electronic Edition (link) BibTeX
- Andy Ye, Jonathan Rose:
Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits.
462-473
Electronic Edition (link) BibTeX
- Andy Yan, Steven J. E. Wilton:
Product-Term-Based Synthesizable Embedded Programmable Logic Cores.
474-488
Electronic Edition (link) BibTeX
- H.-Y. Hsu, J.-C. Yeo, A.-Y. Wu:
Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element.
489-500
Electronic Edition (link) BibTeX
- Wei Huang, Shougata Ghosh, Sivakumar Velusamy, Karthik Sankaranarayanan, Kevin Skadron, Mircea R. Stan:
HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design.
501-513
Electronic Edition (link) BibTeX
- Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.
514-524
Electronic Edition (link) BibTeX
- Yuan Xie, Wayne Wolf, Haris Lekatsas:
Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding.
525-536
Electronic Edition (link) BibTeX
- Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici:
Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison.
537-548
Electronic Edition (link) BibTeX
- J.-J. Kim, K. Roy:
A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.
549-552
Electronic Edition (link) BibTeX
- Eric Wong, Jacob R. Minz, Sung Kyu Lim:
Multi-Objective Module Placement For 3-D System-On-Package.
553-557
Electronic Edition (link) BibTeX
Volume 14,
Number 6,
June 2006
- Foster F. Dai, Charles E. Stroud, Dayu Yang:
Automatic linearity and frequency response tests with built-in pattern generator and analyzer.
561-572
Electronic Edition (link) BibTeX
- Nitin Mohan, W. Fung, Derek Wright, Manoj Sachdev:
Design techniques and test methodology for low-power TCAMs.
573-586
Electronic Edition (link) BibTeX
- Eric MacDonald, Nur A. Touba:
Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits.
587-595
Electronic Edition (link) BibTeX
- Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana:
The LOTTERYBUS on-chip communication architecture.
596-608
Electronic Edition (link) BibTeX
- Byeong Kil Lee, Lizy Kurian John, Eugene John:
Architectural enhancements for network congestion control applications.
609-615
Electronic Edition (link) BibTeX
- Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh:
Power minimization for dynamic PLAs.
616-624
Electronic Edition (link) BibTeX
- Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh K. Gupta:
Energy efficient watermarking on mobile devices using proxy-based partitioning.
625-636
Electronic Edition (link) BibTeX
- Masud H. Chowdhury, Yehea I. Ismail:
Realistic scalability of noise in dynamic circuits.
637-641
Electronic Edition (link) BibTeX
- Junmou Zhang, Eby G. Friedman:
Crosstalk modeling for coupled RLC interconnects with application to shield insertion.
641-646
Electronic Edition (link) BibTeX
- Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
646-649
Electronic Edition (link) BibTeX
- Sunghoon Chun, YongJoon Kim, Jung-Been Im, Sungho Kang:
MICRO: a new hybrid test data compression/decompression scheme.
649-654
Electronic Edition (link) BibTeX
- J. Balachandran, Steven Brebels, G. Carchon, M. Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne:
Wafer-level package interconnect options.
654-659
Electronic Edition (link) BibTeX
- Mohammed Benaissa, Wei Ming Lim:
Design of flexible GF(2m) elliptic curve cryptography processors.
659-662
Electronic Edition (link) BibTeX
Volume 14,
Number 7,
July 2006
- Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo, Giovanni Beltrame, V. Gagne, Gabriela Nicolescu:
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia.
667-680
Electronic Edition (link) BibTeX
- Sungchan Kim, Soonhoi Ha:
Efficient exploration of bus-based system-on-chip architectures.
681-692
Electronic Edition (link) BibTeX
- Ümit Y. Ogras, Radu Marculescu:
"It's a small world after all": NoC performance optimization via long-range link insertion.
693-706
Electronic Edition (link) BibTeX
- Xinping Zhu, Wei Qin, Sharad Malik:
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.
707-716
Electronic Edition (link) BibTeX
- Linwei Niu, Gang Quan:
Energy minimization for real-time systems with (m, k)-guarantee.
717-729
Electronic Edition (link) BibTeX
- Juanjo Noguera, Rosa M. Badia:
System-level power-performance tradeoffs for reconfigurable computing.
730-739
Electronic Edition (link) BibTeX
- Catherine H. Gebotys:
A table masking countermeasure for low-energy secure embedded systems.
740-753
Electronic Edition (link) BibTeX
- Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
754-762
Electronic Edition (link) BibTeX
- Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman:
Extraction error modeling and automated model debugging in high-performance custom designs.
763-776
Electronic Edition (link) BibTeX
- Denis Deschacht:
DSM interconnects: importance of inductance effects and corresponding range of length.
777-779
Electronic Edition (link) BibTeX
- Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang:
Instruction buffering for nested loops in low-power design.
780-784
Electronic Edition (link) BibTeX
Volume 14,
Number 8,
August 2006
- Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau:
Retargetable pipeline hazard detection for partially bypassed processors.
791-801
Electronic Edition (link) BibTeX
- Manish Verma, Peter Marwedel:
Overlay techniques for scratchpad memories in low power embedded processors.
802-815
Electronic Edition (link) BibTeX
- Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran:
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system.
816-829
Electronic Edition (link) BibTeX
- Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau:
Expression equivalence checking using interval analysis.
830-842
Electronic Edition (link) BibTeX
- Soheil Ghiasi, Po-Kuan Huang, Roozbeh Jafari:
Probabilistic delay budget assignment for synthesis of soft real-time applications.
843-853
Electronic Edition (link) BibTeX
- Stephen A. Edwards, Olivier Tardieu:
SHIM: a deterministic model for heterogeneous embedded systems.
854-867
Electronic Edition (link) BibTeX
- JoAnn M. Paul, Donald E. Thomas, Alex Bobrek:
Scenario-oriented design for single-chip heterogeneous multiprocessors.
868-880
Electronic Edition (link) BibTeX
- Lihong Zhang, Ulrich Kleine, Yingtao Jiang:
An automated design tool for analog layouts.
881-894
Electronic Edition (link) BibTeX
- V. Chaudhary, Lawrence T. Clark:
Low-power high-performance nand match line content addressable memories.
895-905
Electronic Edition (link) BibTeX
- I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson:
Placement for large-scale floating-gate field-programable analog arrays.
906-910
Electronic Edition (link) BibTeX
- Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors.
910-915
Electronic Edition (link) BibTeX
- Jae Hyun Baek, Myung Hoon Sunwoo:
New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder.
915-920
Electronic Edition (link) BibTeX
Volume 14,
Number 9,
September 2006
- Ming-Bo Lin, Jang-Feng Lee, Gene Eu Jan:
A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture.
925-936
Electronic Edition (link) BibTeX
- Zhongfeng Wang, Jun Ma:
High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes.
937-950
Electronic Edition (link) BibTeX
- Hooman Nikmehr, Braden Phillips, Cheng-Chew Lim:
Fast Decimal Floating-Point Division.
951-961
Electronic Edition (link) BibTeX
- Minghua Shi, Amine Bermak:
An Efficient Digital VLSI Implementation of Gaussian Mixture Models-Based Classifier.
962-974
Electronic Edition (link) BibTeX
- Recep O. Ozdag, Peter A. Beerel:
An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates.
975-985
Electronic Edition (link) BibTeX
- Jason Cong, Guoling Han, Zhiru Zhang:
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors.
986-997
Electronic Edition (link) BibTeX
- Yajun Ran, Malgorzata Marek-Sadowska:
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics.
998-1009
Electronic Edition (link) BibTeX
- K. N. Vikram, V. Vasudevan:
Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures.
1010-1023
Electronic Edition (link) BibTeX
- Mehdi Baradaran Tahoori:
Application-Dependent Testing of FPGAs.
1024-1033
Electronic Edition (link) BibTeX
- Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
1034-1039
Electronic Edition (link) BibTeX
- Madhavi Gopal Valluri, Lizy Kurian John, Heather Hanson:
Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors.
1039-1043
Electronic Edition (link) BibTeX
- Ilya Obridko, Ran Ginosar:
Minimal Energy Asynchronous Dynamic Adders.
1043-1047
Electronic Edition (link) BibTeX
Volume 14,
Number 10,
October 2006
- Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa:
Efficient Synchronization for Embedded On-Chip Multiprocessors.
1049-1062
Electronic Edition (link) BibTeX
- Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou:
High Rate Data Synchronization in GALS SoCs.
1063-1074
Electronic Edition (link) BibTeX
- Dongwoo Lee, David Blaauw, Dennis Sylvester:
Runtime Leakage Minimization Through Probability-Aware Optimization.
1075-1088
Electronic Edition (link) BibTeX
- K.-S. Hsiao, C.-H. Chen:
Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation.
1089-1102
Electronic Edition (link) BibTeX
- Ali Iranli, Wonbok Lee, Massoud Pedram:
HVS-Aware Dynamic Backlight Scaling in TFT-LCDs.
1103-1116
Electronic Edition (link) BibTeX
- Luis Alejandro Cortés, Petru Eles, Zebo Peng:
Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations.
1117-1129
Electronic Edition (link) BibTeX
- Thara Rejimon, Sanjukta Bhanja:
A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis.
1130-1139
Electronic Edition (link) BibTeX
- Debjit Sinha, Narendra V. Shenoy, Hai Zhou:
Statistical Timing Yield Optimization by Gate Sizing.
1140-1146
Electronic Edition (link) BibTeX
- Zhiyong He, Paul Fortier, Sébastien Roy:
Highly-Parallel Decoding Architectures for Convolutional Turbo Codes.
1147-1151
Electronic Edition (link) BibTeX
- Mohammad Maymandi-Nejad, Manoj Sachdev:
DTMOS Technique for Low-Voltage Analog Circuits.
1151-1156
Electronic Edition (link) BibTeX
- X. Zhang:
Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding.
1156-1161
Electronic Edition (link) BibTeX
Volume 14,
Number 11,
November 2006
- Rajarshi Mukherjee, Seda Ogrenci Memik:
An Integrated Approach to Thermal Management in High-Level Synthesis.
1165-1174
Electronic Edition (link) BibTeX
- Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Scalable Synthesis Methodology for Application-Specific Processors.
1175-1188
Electronic Edition (link) BibTeX
- Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt:
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration.
1189-1202
Electronic Edition (link) BibTeX
- Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.
1203-1215
Electronic Edition (link) BibTeX
- Haihua Yan, Adit D. Singh:
A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI).
1216-1226
Electronic Edition (link) BibTeX
- Kedarnath J. Balakrishnan, Nur A. Touba:
Improving Linear Test Data Compression.
1227-1237
Electronic Edition (link) BibTeX
- Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.
1238-1249
Electronic Edition (link) BibTeX
- Jun-Cheol Park, Vincent John Mooney III:
Sleepy Stack Leakage Reduction.
1250-1263
Electronic Edition (link) BibTeX
- Chuan Lin, Jia Wang, Hai Zhou:
Clustering for Processing Rate Optimization.
1264-1275
Electronic Edition (link) BibTeX
- Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.
1276-1281
Electronic Edition (link) BibTeX
- Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan:
Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective.
1281-1286
Electronic Edition (link) BibTeX
- Thomas Lenart, Viktor Öwall:
Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores.
1286-1290
Electronic Edition (link) BibTeX
Volume 14,
Number 12,
December 2006
- Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.
1295-1308
Electronic Edition (link) BibTeX
- Sumeer Goel, Ashok Kumar, Magdy A. Bayoumi:
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.
1309-1321
Electronic Edition (link) BibTeX
- Massimo Alioto, Gaetano Palumbo:
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.
1322-1335
Electronic Edition (link) BibTeX
- Mark M. Budnik, Kaushik Roy:
A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.
1336-1346
Electronic Edition (link) BibTeX
- Erik J. Mentze, Herbert L. Hess, Kevin M. Buck, T. G. Windley:
A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies.
1347-1353
Electronic Edition (link) BibTeX
- Kambiz Rahimi, Chris Diorio:
Design and Application of Adaptive Delay Sequential Elements.
1354-1367
Electronic Edition (link) BibTeX
- Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel:
Sequential Element Design With Built-In Soft Error Resilience.
1368-1378
Electronic Edition (link) BibTeX
- C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, Y. Oowaki:
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.
1379-1383
Electronic Edition (link) BibTeX
- Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap:
Fast Interconnect and Gate Timing Analysis for Performance Optimization.
1383-1388
Electronic Edition (link) BibTeX
- José Luis Imaña, Román Hermida, Francisco Tirado:
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.
1388-1393
Electronic Edition (link) BibTeX
- Mosin Mondal, Yehia Massoud:
Accurate Loop Self Inductance Bound for Efficient Inductance Screening.
1393-1397
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:31:00 2009
by Michael Ley (ley@uni-trier.de)
