| 2006 |
|---|
| 9 | EE | Denis Deschacht:
DSM interconnects: importance of inductance effects and corresponding range of length.
IEEE Trans. VLSI Syst. 14(7): 777-779 (2006) |
| 2005 |
|---|
| 8 | EE | Denis Deschacht,
Alain Lopez:
Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation.
VLSI Design 2005: 640-643 |
| 2004 |
|---|
| 7 | EE | Alain Lopez,
Denis Deschacht:
Comparison between Different Data Buses Configurations.
ISVLSI 2004: 69-76 |
| 2002 |
|---|
| 6 | EE | Grégory Servel,
Denis Deschacht,
Françoise Saliou,
Jean-Luc Mattei,
Fabrice Huret:
Impact of Low-K on Crosstalk.
ISQED 2002: 298-303 |
| 2001 |
|---|
| 5 | EE | Denis Deschacht,
Grégory Servel:
On-chip interconnections: impact of adjacent lines on timing.
ASP-DAC 2001: 539-544 |
| 2000 |
|---|
| 4 | EE | Denis Deschacht,
Grégory Servel,
Fabrice Huret,
Erick Paleczny,
Patrick Kennis:
Theoretical limits for signal reflections due to inductance for on-chip interconnections.
SLIP 2000: 55-60 |
| 1995 |
|---|
| 3 | EE | Denis Deschacht,
Christophe Dabrin:
A new and accurate interconnection delay time evaluation in a general tree-type network.
ASP-DAC 1995 |
| 1993 |
|---|
| 2 | EE | Denis Deschacht,
Michel Robert,
Nadine Azémard-Crestani,
Daniel Auvergne:
Post-layout timing simulation of CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1170-1177 (1993) |
| 1990 |
|---|
| 1 | EE | Denis Deschacht,
P. Pinede,
Michel Robert,
Daniel Auvergne:
Path runner: an accurate and fast timing analyser.
EURO-DAC 1990: 529-533 |
