| 2008 |
|---|
| 57 | EE | Massimo Alioto,
Gaetano Palumbo:
Power-delay optimization in MCML tapered buffers.
ISCAS 2008: 141-144 |
| 56 | EE | Gianluca Giustolisi,
Gaetano Palumbo,
Ester Spitale:
Low-voltage LDO Compensation Strategy based on Current Amplifiers.
ISCAS 2008: 2681-2684 |
| 55 | EE | Massimo Alioto,
Massimo Poli,
Gaetano Palumbo:
Explicit energy evaluation in RLC tree circuits with ramp inputs.
ISCAS 2008: 2865-2868 |
| 54 | EE | Massimo Alioto,
Gaetano Palumbo,
Melita Pennisi:
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.
PATMOS 2008: 136-145 |
| 53 | EE | Gaetano Palumbo,
Melita Pennisi:
AMOLED pixel driver circuits based on poly-Si TFTs: A comparison.
Integration 41(3): 439-446 (2008) |
| 2007 |
|---|
| 52 | EE | Christian Falconi,
Arnaldo D'Amico,
Gianluca Giustolisi,
Gaetano Palumbo:
Rosenstark-like Representation of Feedback Amplifier Resistance.
ISCAS 2007: 2212-2215 |
| 51 | EE | Walter Aloisi,
Giuseppe Di Cataldo,
Gaetano Palumbo,
Salvatore Pennisi:
Miller Compensation: Optimization with Current Buffer/Amplifier.
ISCAS 2007: 2216-2219 |
| 50 | EE | Massimo Alioto,
Gaetano Palumbo:
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.
ISCAS 2007: 2998-3001 |
| 49 | EE | Massimo Alioto,
Gaetano Palumbo:
Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.
ISCAS 2007: 3255-3258 |
| 48 | EE | Massimo Alioto,
Gaetano Palumbo:
Delay Variability Due to Supply Variations in Transmission-Gate Full Adders.
ISCAS 2007: 3732-3735 |
| 47 | EE | Massimo Alioto,
Giuseppe Di Cataldo,
Gaetano Palumbo:
Mixed Full Adder topologies for high-performance low-power arithmetic circuits.
Microelectronics Journal 38(1): 130-139 (2007) |
| 2006 |
|---|
| 46 | EE | A. D. Grasso,
Gaetano Palumbo,
Salvatore Pennisi:
Active reversed nested Miller compensation for three-stage amplifiers.
ISCAS 2006 |
| 45 | EE | Gaetano Palumbo,
Melita Pennisi,
Salvatore Pennisi:
Analysis and evaluation of harmonic distortion in the tunnel diode oscillator.
ISCAS 2006 |
| 44 | EE | Massimo Alioto,
Gaetano Palumbo:
Delay uncertainty due to supply variations in static and dynamic full adders.
ISCAS 2006 |
| 43 | EE | Massimo Alioto,
Gaetano Palumbo,
Massimo Poli:
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.
ISCAS 2006 |
| 42 | EE | Massimo Alioto,
Gaetano Palumbo:
Nanometer MCML gates: models and design considerations.
ISCAS 2006 |
| 41 | EE | Massimo Alioto,
Gaetano Palumbo:
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.
IEEE Trans. VLSI Syst. 14(12): 1322-1335 (2006) |
| 40 | EE | Massimo Alioto,
Gaetano Palumbo,
Massimo Poli:
Energy Consumption in RC Tree Circuits.
IEEE Trans. VLSI Syst. 14(5): 452-461 (2006) |
| 39 | EE | Rosario Mita,
Gaetano Palumbo,
Pier Giorgio Fallica:
A fast driver circuit for single-photon sensors.
Microelectronics Journal 37(10): 1092-1096 (2006) |
| 2005 |
|---|
| 38 | EE | Rosario Mita,
Gaetano Palumbo,
Salvatore Pennisi:
Well-defined design procedure for a three-stage CMOS OTA.
ISCAS (3) 2005: 2579-2582 |
| 37 | EE | Massimo Alioto,
Gaetano Palumbo:
Design techniques for low-power cascaded CML gates.
ISCAS (5) 2005: 4685-4688 |
| 36 | EE | Massimo Alioto,
Gaetano Palumbo,
Massimo Poli:
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.
PATMOS 2005: 355-363 |
| 2004 |
|---|
| 35 | EE | Walter Aloisi,
Stello Matteo Billé,
Gaetano Palumbo:
Low-voltage linear voltage regulator suitable for memories.
ISCAS (1) 2004: 389-392 |
| 34 | EE | Gaetano Palumbo,
Salvatore Pennisi:
Harmonic distortion in three-stage nested-Miller-compensated amplifiers.
ISCAS (1) 2004: 485-488 |
| 33 | | Massimo Alioto,
Gaetano Palumbo,
Massimo Poli:
A gate-level strategy to design Carry Select Adders.
ISCAS (2) 2004: 465-468 |
| 32 | | Gianluca Giustolisi,
Gaetano Palumbo:
Sigma-Delta A/D fuzzy converter.
ISCAS (4) 2004: 677-680 |
| 31 | EE | Massimo Alioto,
Gaetano Palumbo,
Massimo Poli:
Evaluation of energy consumption in RC ladder circuits driven by a ramp input.
IEEE Trans. VLSI Syst. 12(10): 1094-1107 (2004) |
| 2003 |
|---|
| 30 | EE | Gianluca Giustolisi,
Gaetano Palumbo:
A novel 1-V class-AB transconductor for improving speed performance in SC applications.
ISCAS (1) 2003: 153-156 |
| 29 | EE | Walter Aloisi,
Gianluca Giustolisi,
Gaetano Palumbo:
A 1-V CMOS output stage with high linearity.
ISCAS (1) 2003: 225-228 |
| 28 | EE | Gianluca Giustolisi,
Gaetano Palumbo:
A new method for evaluating harmonic distortion in push-pull output stages.
ISCAS (1) 2003: 233-236 |
| 27 | EE | Rosario Mita,
Gaetano Palumbo,
Salvatore Pennisi:
Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs.
ISCAS (1) 2003: 525-528 |
| 26 | EE | Walter Aloisi,
Gianluca Giustolisi,
Gaetano Palumbo:
Design of low-voltage low-power SC filters for high-frequency applications.
ISCAS (1) 2003: 605-608 |
| 25 | EE | Massimo Alioto,
Gaetano Palumbo:
Design of MUX, XOR and D-latch SCL gates.
ISCAS (5) 2003: 261-264 |
| 24 | EE | Massimo Alioto,
Rosario Mita,
Gaetano Palumbo:
Performance evaluation of the low-voltage CML D-latch topology.
Integration 36(4): 191-209 (2003) |
| 2002 |
|---|
| 23 | EE | Giuseppe Notarangelo,
Marco Gibilaro,
Francesco Pappalardo,
Agatino Pennisi,
Gaetano Palumbo:
Low Power Strategy for a TFT Controller.
DSD 2002: 351-354 |
| 22 | EE | Walter Aloisi,
Gianluca Giustolisi,
Gaetano Palumbo:
Analysis and optimization of gain-boosted telescopic amplifiers.
ISCAS (1) 2002: 321-324 |
| 21 | EE | Gianluca Giustolisi,
Gaetano Palumbo:
Analysis of power supply noise attenuation in a PTAT current source.
ISCAS (1) 2002: 561-564 |
| 20 | EE | Massimo Alioto,
Gaetano Palumbo:
Power-delay trade-offs in SCL gates.
ISCAS (3) 2002: 249-252 |
| 19 | EE | Gaetano Palumbo,
F. Pappalardo,
S. Sannella:
Evaluation on power reduction applying gated clock approaches.
ISCAS (4) 2002: 85-88 |
| 18 | EE | Massimo Alioto,
Gaetano Palumbo,
Massimo Poli:
An Approach to Energy Consumption Modeling in RC Ladder Circuits.
PATMOS 2002: 239-246 |
| 17 | EE | Massimo Alioto,
Gaetano Palumbo:
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.
PATMOS 2002: 429-437 |
| 16 | EE | Rosario Mita,
Gaetano Palumbo:
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input.
PATMOS 2002: 468-476 |
| 15 | EE | Massimo Alioto,
Gaetano Palumbo:
Analysis and comparison on full adder block in submicron technology.
IEEE Trans. VLSI Syst. 10(6): 806-823 (2002) |
| 2001 |
|---|
| 14 | EE | Gaetano Palumbo,
Giuseppe Introvaia,
Vincenzo Mastrocola,
Promod Kumar,
Francesco Pipiton:
Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory.
IOLTW 2001: 192-196 |
| 13 | EE | Rosario Mita,
Gaetano Palumbo,
Salvatore Pennisi:
Reversed nested Miller compensation with current follower.
ISCAS (1) 2001: 308-311 |
| 12 | EE | Gianluca Giustolisi,
Gaetano Palumbo:
Detailed frequency analysis of power supply rejection in Brokaw bandgap.
ISCAS (1) 2001: 731-734 |
| 11 | EE | Massimo Alioto,
Giuseppe Di Cataldo,
Gaetano Palumbo:
CML ring oscillators: oscillation frequency.
ISCAS (4) 2001: 112-115 |
| 10 | EE | Gaetano Palumbo,
D. Pappalardo,
M. Gaibotti:
Modeling and minimization of power consumption in charge pump circuits.
ISCAS (4) 2001: 402-405 |
| 9 | EE | Massimo Alioto,
Gaetano Palumbo:
Power estimation in adiabatic circuits: a simple and accurate model.
IEEE Trans. VLSI Syst. 9(5): 608-615 (2001) |
| 2000 |
|---|
| 8 | EE | Massimo Alioto,
Gaetano Palumbo:
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.
PATMOS 2000: 265-275 |
| 1999 |
|---|
| 7 | EE | Massimo Alioto,
Gaetano Palumbo:
Highly accurate and simple models for CML and ECL gates.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1369-1375 (1999) |
| 1998 |
|---|
| 6 | EE | Gianluca Giustolisi,
Giovanni Palmisano,
Gaetano Palumbo,
C. Strano:
A Novel 1.5-V Cmos Mixer.
Great Lakes Symposium on VLSI 1998: 113-117 |
| 5 | EE | Massimo Alioto,
Gaetano Palumbo:
Novel Simple Models Of Cml Propagation Delay.
Great Lakes Symposium on VLSI 1998: 270-274 |
| 1995 |
|---|
| 4 | | Giuseppe Di Cataldo,
Giovanni Palmisano,
Gaetano Palumbo:
A CMOS CCII+.
ISCAS 1995: 315-318 |
| 1994 |
|---|
| 3 | | Gaetano Palumbo:
Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling time.
ISCAS 1994: 413-416 |
| 2 | | Giuseppe Di Cataldo,
Gaetano Palumbo:
Optimized Design of 4 Stage Dickson Voltage Multiplier.
ISCAS 1994: 693-696 |
| 1 | | Giovanni Palmisano,
Gaetano Palumbo,
Salvatore Pennisi:
A High-Accuracy High-Speed CMOS Current Comparator.
ISCAS 1994: 739-742 |
