Massimo Alioto

2008
41	EE	Massimo Alioto, Gaetano Palumbo: Power-delay optimization in MCML tapered buffers. ISCAS 2008: 141-144
40	EE	Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer: Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148
39	EE	Massimo Alioto, Luca Fondelli, Santina Rocchi: Analysis and performance evaluation of area-efficient true random bit generators on FPGAs. ISCAS 2008: 1572-1575
38	EE	Massimo Alioto, Massimo Poli, Gaetano Palumbo: Explicit energy evaluation in RLC tree circuits with ramp inputs. ISCAS 2008: 2865-2868
37	EE	Massimo Alioto, Massimo Poli, Santina Rocchi: A general model for differential power analysis attacks to static logic circuits. ISCAS 2008: 3346-3349
36	EE	Massimo Alioto, Gaetano Palumbo, Melita Pennisi: Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. PATMOS 2008: 136-145
35	EE	Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici: Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS 2008: 21-30
34	EE	Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi: Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. PATMOS 2008: 31-41
2007
33	EE	Massimo Alioto, Gaetano Palumbo: High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. ISCAS 2007: 2998-3001
32	EE	Massimo Alioto, Gaetano Palumbo: Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. ISCAS 2007: 3255-3258
31	EE	Massimo Alioto, Gaetano Palumbo: Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. ISCAS 2007: 3732-3735
30	EE	Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli: Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map. ISCAS 2007: 693-696
29	EE	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli: Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. ISCAS 2007: 861-864
28	EE	Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo: Mixed Full Adder topologies for high-performance low-power arithmetic circuits. Microelectronics Journal 38(1): 130-139 (2007)
2006
27	EE	Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli: A technique to design high entropy chaos-based true random bit generators. ISCAS 2006
26	EE	Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli: Analysis and design of MCML gates with hysteresis. ISCAS 2006
25	EE	Massimo Alioto, Gaetano Palumbo: Delay uncertainty due to supply variations in static and dynamic full adders. ISCAS 2006
24	EE	Massimo Alioto, Gaetano Palumbo, Massimo Poli: Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. ISCAS 2006
23	EE	Massimo Alioto, Gaetano Palumbo: Nanometer MCML gates: models and design considerations. ISCAS 2006
22	EE	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli: Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. PATMOS 2006: 593-602
21	EE	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli: Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. PATMOS 2006: 624-633
20	EE	Massimo Alioto, Gaetano Palumbo: Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. IEEE Trans. VLSI Syst. 14(12): 1322-1335 (2006)
19	EE	Massimo Alioto, Gaetano Palumbo, Massimo Poli: Energy Consumption in RC Tree Circuits. IEEE Trans. VLSI Syst. 14(5): 452-461 (2006)
2005
18	EE	Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli: Long period pseudo random bit generators derived from a discretized chaotic map. ISCAS (2) 2005: 892-895
17	EE	Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli: An approach to the design of PFSCL gates. ISCAS (3) 2005: 2437-2440
16	EE	Massimo Alioto, Gaetano Palumbo: Design techniques for low-power cascaded CML gates. ISCAS (5) 2005: 4685-4688
15	EE	Massimo Alioto, Gaetano Palumbo, Massimo Poli: Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. PATMOS 2005: 355-363
2004
14		Massimo Alioto, Gaetano Palumbo, Massimo Poli: A gate-level strategy to design Carry Select Adders. ISCAS (2) 2004: 465-468
13		Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli: Positive-Feedback Source-Coupled Logic: a delay model. ISCAS (2) 2004: 641-644
12	EE	Massimo Alioto, Gaetano Palumbo, Massimo Poli: Evaluation of energy consumption in RC ladder circuits driven by a ramp input. IEEE Trans. VLSI Syst. 12(10): 1094-1107 (2004)
2003
11	EE	Massimo Alioto, Gaetano Palumbo: Design of MUX, XOR and D-latch SCL gates. ISCAS (5) 2003: 261-264
10	EE	Massimo Alioto, Rosario Mita, Gaetano Palumbo: Performance evaluation of the low-voltage CML D-latch topology. Integration 36(4): 191-209 (2003)
2002
9	EE	Massimo Alioto, Gaetano Palumbo: Power-delay trade-offs in SCL gates. ISCAS (3) 2002: 249-252
8	EE	Massimo Alioto, Gaetano Palumbo, Massimo Poli: An Approach to Energy Consumption Modeling in RC Ladder Circuits. PATMOS 2002: 239-246
7	EE	Massimo Alioto, Gaetano Palumbo: Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. PATMOS 2002: 429-437
6	EE	Massimo Alioto, Gaetano Palumbo: Analysis and comparison on full adder block in submicron technology. IEEE Trans. VLSI Syst. 10(6): 806-823 (2002)
2001
5	EE	Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo: CML ring oscillators: oscillation frequency. ISCAS (4) 2001: 112-115
4	EE	Massimo Alioto, Gaetano Palumbo: Power estimation in adiabatic circuits: a simple and accurate model. IEEE Trans. VLSI Syst. 9(5): 608-615 (2001)
2000
3	EE	Massimo Alioto, Gaetano Palumbo: Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. PATMOS 2000: 265-275
1999
2	EE	Massimo Alioto, Gaetano Palumbo: Highly accurate and simple models for CML and ECL gates. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1369-1375 (1999)
1998
1	EE	Massimo Alioto, Gaetano Palumbo: Novel Simple Models Of Cml Propagation Delay. Great Lakes Symposium on VLSI 1998: 270-274

Coauthor Index

1	Tommaso Addabbo	[18] [27] [30]
2	Matteo Agostinelli	[34]
3	Elizabeth J. Brauer	[35] [40]
4	Giuseppe Di Cataldo	[5] [28]
5	David Esseni	[34]
6	Luca Fondelli	[39]
7	Ada Fort	[13] [17] [18] [27] [30]
8	Frank K. Gürkaynak	[40]
9	Yusuf Leblebici	[35] [40]
10	Rosario Mita	[10]
11	Gaetano Palumbo	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [16] [19] [20] [23] [24] [25] [28] [31] [32] [33] [36] [38] [41]
12	Luca Pancioni	[13] [17] [26]
13	Melita Pennisi	[36]
14	Massimo Poli	[8] [12] [14] [15] [19] [21] [22] [24] [29] [37] [38]
15	Santina Rocchi	[13] [17] [18] [21] [22] [26] [27] [29] [30] [37] [39]
16	Luca Selmi	[34]
17	Armin Tajalli	[35] [40]
18	Valerio Vignoli	[13] [17] [18] [21] [22] [26] [27] [29] [30]

Colors in the list of coauthors