| 2008 |
|---|
| 8 | EE | Byung-Do Yang,
Jang-Su Kim,
Jin-Kuk Yun,
Yong-Kyu Lee,
Jee-Sue Lee:
A highly accurate BiCMOS cascode current mirror for wide output voltage range.
ISCAS 2008: 2314-2317 |
| 2007 |
|---|
| 7 | EE | Byung-Do Yang,
Jae-Eun Lee,
Jang-Su Kim,
Junghyun Cho,
Seung-Yun Lee,
Byoung-Gon Yu:
A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme.
ISCAS 2007: 3014-3017 |
| 2006 |
|---|
| 6 | EE | Byung-Do Yang,
Lee-Sup Kim:
A low-power ROM using single charge-sharing capacitor and hierarchical bit line.
IEEE Trans. VLSI Syst. 14(4): 313-322 (2006) |
| 2004 |
|---|
| 5 | | Byung-Do Yang,
Lee-Sup Kim:
An error pattern ROM compression method for continuous data.
ISCAS (2) 2004: 845-848 |
| 2003 |
|---|
| 4 | EE | Byung-Do Yang,
Lee-Sup Kim:
A low power charge sharing ROM using dummy bit lines.
ISCAS (5) 2003: 377-380 |
| 3 | EE | Byung-Do Yang,
Lee-Sup Kim:
A low-power charge-recycling ROM architecture.
IEEE Trans. VLSI Syst. 11(4): 590-600 (2003) |
| 2002 |
|---|
| 2 | EE | Byung-Do Yang,
Lee-Sup Kim,
Hyun-Kyu Yu:
A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator.
ISCAS (5) 2002: 373-376 |
| 2001 |
|---|
| 1 | EE | Byung-Do Yang,
Lee-Sup Kim:
A low power charge-recycling ROM architecture.
ISCAS (4) 2001: 510-513 |
