2009 |
32 | EE | Sohan Purohit,
Martin Margala,
Marco Lanuzza,
Pasquale Corsonello:
New performance/power/area efficient, reliable full adder design.
ACM Great Lakes Symposium on VLSI 2009: 493-498 |
31 | EE | Marco Lanuzza,
Paolo Zicari,
Fabio Frustaci,
Stefania Perri,
Pasquale Corsonello:
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.
ARC 2009: 74-84 |
30 | EE | Sohan Purohit,
Marco Lanuzza,
Stefania Perri,
Pasquale Corsonello,
Martin Margala:
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
VLSI Design 2009: 45-50 |
2008 |
29 | EE | Fabio Frustaci,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.
PATMOS 2008: 277-286 |
28 | EE | Marco Lanuzza,
Stefania Perri,
Pasquale Corsonello,
Martin Margala:
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.
PATMOS 2008: 297-306 |
27 | EE | Sohan Purohit,
Sai Rahul Chalamalasetti,
Martin Margala,
Pasquale Corsonello:
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing.
SoCC 2008: 375-378 |
26 | EE | Paolo Zicari,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
A matrix product accelerator for field programmable systems on chip.
Microprocessors and Microsystems - Embedded Hardware Design 32(2): 53-67 (2008) |
25 | EE | Paolo Zicari,
Emanuele Sciagura,
Stefania Perri,
Pasquale Corsonello:
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals.
Microprocessors and Microsystems - Embedded Hardware Design 32(8): 437-446 (2008) |
2007 |
24 | EE | Marco Lanuzza,
Stefania Perri,
Pasquale Corsonello,
Martin Margala:
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications.
AHS 2007: 119-126 |
23 | EE | Emanuele Sciagura,
Paolo Zicari,
Stefania Perri,
Pasquale Corsonello:
An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.
DSD 2007: 102-108 |
22 | EE | Pasquale Corsonello,
Stefania Perri,
G. Staino,
Marco Lanuzza,
Giuseppe Cocorullo:
Design and Implementation of a 90nm Low bit-rate Image Compression Core.
DSD 2007: 383-389 |
21 | EE | Marco Lanuzza,
Stefania Perri,
Pasquale Corsonello:
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing.
SAMOS 2007: 159-168 |
2006 |
20 | EE | Pasquale Corsonello,
Stefania Perri,
Martin Margala:
An integrated countermeasure against differential power analysis for secure smart-cards.
ISCAS 2006 |
19 | EE | Fabio Frustaci,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
Leakage energy reduction techniques in deep submicron cache memories: a comparative study.
ISCAS 2006 |
18 | EE | Pasquale Corsonello,
Stefania Perri,
G. Staino,
Marco Lanuzza,
Giuseppe Cocorullo:
Low bit rate image compression core for onboard space applications.
IEEE Trans. Circuits Syst. Video Techn. 16(1): 114-128 (2006) |
17 | EE | Fabio Frustaci,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.
IEEE Trans. VLSI Syst. 14(11): 1238-1249 (2006) |
16 | EE | Stefania Perri,
Maria Antonia Iachino,
Pasquale Corsonello:
Simd Multipliers for Accelerating Embedded Processors in FPGAS.
Journal of Circuits, Systems, and Computers 15(4): 537-550 (2006) |
2005 |
15 | | Marco Lanuzza,
Stefania Perri,
Martin Margala,
Pasquale Corsonello:
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor.
FPL 2005: 13-18 |
14 | EE | Marco Lanuzza,
Martin Margala,
Pasquale Corsonello:
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.
ISLPED 2005: 161-166 |
13 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
Fast Low-Power 64-Bit Modular Hybrid Adder.
PATMOS 2005: 609-617 |
12 | EE | Pasquale Corsonello,
Stefania Perri:
Efficient Reconfigurable Manchester Adders for Low-power Media Processing.
Journal of Circuits, Systems, and Computers 14(1): 57-64 (2005) |
11 | EE | Pasquale Corsonello,
Stefania Perri,
Paolo Zicari,
Giuseppe Cocorullo:
Microprocessor-based FPGA implementation of SPIHT image compression subsystems.
Microprocessors and Microsystems 29(6): 299-305 (2005) |
10 | EE | Stefania Perri,
Marco Lanuzza,
Pasquale Corsonello,
Giuseppe Cocorullo:
A high-performance fully reconfigurable FPGA-based 2D convolution processor.
Microprocessors and Microsystems 29(8-9): 381-391 (2005) |
2004 |
9 | | Pasquale Corsonello,
Stefania Perri,
Vitit Kantabutra:
Area- and Power-Reduced Standard-Cell Spanning Tree Adders.
ESA/VLSI 2004: 343-352 |
8 | EE | Stefania Perri,
Pasquale Corsonello,
Maria Antonia Iachino,
Marco Lanuzza,
Giuseppe Cocorullo:
Variable precision arithmetic circuits for FPGA-based multimedia processors.
IEEE Trans. VLSI Syst. 12(9): 995-999 (2004) |
2003 |
7 | EE | Pasquale Corsonello,
Stefania Perri,
Maria Antonia Iachino,
Giuseppe Cocorullo:
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems.
FPL 2003: 661-669 |
6 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
A high-speed energy-efficient 64-bit reconfigurable binary adder.
IEEE Trans. VLSI Syst. 11(5): 939-943 (2003) |
2002 |
5 | EE | Pasquale Corsonello,
Giandomenico Spezzano,
G. Staino,
Domenico Talia:
Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware.
PDP 2002: 211-218 |
4 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
VLSI circuits for low-power high-speed asynchronous addition.
IEEE Trans. VLSI Syst. 10(5): 608-613 (2002) |
2000 |
3 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
Designing High-Speed Asynchronous Pipelines.
EUROMICRO 2000: 1394-1399 |
2 | EE | Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.
PATMOS 2000: 195-204 |
1 | EE | Pasquale Corsonello,
Stefania Perri,
G. Cororullo:
Area-time-power tradeoff in cellular arrays VLSI implementations.
IEEE Trans. VLSI Syst. 8(5): 614-624 (2000) |