| 2008 |
|---|
| 9 | EE | Arkadiy Morgenshtein,
Eby G. Friedman,
Ran Ginosar,
Avinoam Kolodny:
Timing optimization in logic with interconnect.
SLIP 2008: 19-26 |
| 8 | EE | Rostislav (Reuven) Dobkin,
Arkadiy Morgenshtein,
Avinoam Kolodny,
Ran Ginosar:
Parallel vs. serial on-chip communication.
SLIP 2008: 43-50 |
| 2006 |
|---|
| 7 | EE | Michael Moreinis,
Arkadiy Morgenshtein,
Israel A. Wagner,
Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.
IEEE Trans. VLSI Syst. 14(11): 1276-1281 (2006) |
| 2005 |
|---|
| 6 | EE | Arkadiy Morgenshtein,
Israel Cidon,
Ran Ginosar,
Avinoam Kolodny:
Low-leakage repeaters for NoC interconnects.
ISCAS (1) 2005: 600-603 |
| 2004 |
|---|
| 5 | | Arkadiy Morgenshtein,
Alexander Fish,
Israel A. Wagner:
An efficient implementation of D-Flip-Flop using the GDI technique.
ISCAS (2) 2004: 673-676 |
| 4 | EE | Arkadiy Morgenshtein,
Michael Moreinis,
Ran Ginosar:
Asynchronous gate-diffusion-input (GDI) circuits.
IEEE Trans. VLSI Syst. 12(8): 847-856 (2004) |
| 2003 |
|---|
| 3 | | Arkadiy Morgenshtein,
Michael Moreinis,
Israel A. Wagner,
Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.
VLSI-SOC 2003: 99-104 |
| 2002 |
|---|
| 2 | EE | Arkadiy Morgenshtein,
Alexander Fish,
Israel A. Wagner:
Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization.
ISCAS (1) 2002: 477-480 |
| 1 | EE | Arkadiy Morgenshtein,
Alexander Fish,
Israel A. Wagner:
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits.
IEEE Trans. VLSI Syst. 10(5): 566-581 (2002) |
