| 2009 |
|---|
| 49 | EE | Amir Khatib Zadeh,
Catherine H. Gebotys:
Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC).
ISQED 2009: 230-235 |
| 48 | EE | Patrick Longa,
Catherine H. Gebotys:
Fast Multibase Methods and Other Several Optimizations for Elliptic Curve Scalar Multiplication.
Public Key Cryptography 2009: 443-462 |
| 47 | EE | Reouven Elbaz,
David Champagne,
Catherine H. Gebotys,
Ruby B. Lee,
Nachiketh R. Potlapally,
Lionel Torres:
Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines.
Transactions on Computational Science 4: 1-22 (2009) |
| 2008 |
|---|
| 46 | | Catherine H. Gebotys,
Grant Martin:
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008
ACM 2008 |
| 45 | EE | Catherine H. Gebotys,
Brian A. White:
EM analysis of a wireless Java-based PDA.
ACM Trans. Embedded Comput. Syst. 7(4): (2008) |
| 2007 |
|---|
| 44 | EE | Catherine H. Gebotys,
Brian A. White:
A Phase Substitution Technique for DEMA of Embedded Cryptographic Systems.
ITNG 2007: 868-869 |
| 43 | EE | Amir Khatibzadeh,
Catherine H. Gebotys:
Enhanced Current-Balanced Logic (ECBL): An Area Efficient Solution to Secure Smart Cards against Differential Power Attack.
ITNG 2007: 898-899 |
| 2006 |
|---|
| 42 | EE | Catherine H. Gebotys,
Brian A. White:
Methodology for attack on a Java-based PDA.
CODES+ISSS 2006: 94-99 |
| 41 | EE | Catherine H. Gebotys:
A split-mask countermeasure for low-energy secure embedded systems.
ACM Trans. Embedded Comput. Syst. 5(3): 577-612 (2006) |
| 40 | EE | Catherine H. Gebotys:
A table masking countermeasure for low-energy secure embedded systems.
IEEE Trans. VLSI Syst. 14(7): 740-753 (2006) |
| 2005 |
|---|
| 39 | EE | Catherine H. Gebotys,
Simon Ho,
C. C. Tiu:
EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA.
CHES 2005: 250-264 |
| 38 | EE | Catherine H. Gebotys,
C. C. Tiu,
X. Chen:
A Countermeasure for EM Attack of a Wireless PDA.
ITCC (1) 2005: 544-549 |
| 37 | EE | Tim Woo,
Catherine H. Gebotys,
Sagar Naik:
An Energy-Efficient Image Representation for Secure Mobile Systems.
NETWORKING 2005: 126-137 |
| 36 | EE | Radu Muresan,
Catherine H. Gebotys:
Instantaneous current modeling in a complex VLIW processor core.
ACM Trans. Embedded Comput. Syst. 4(2): 415-451 (2005) |
| 2004 |
|---|
| 35 | EE | Radu Muresan,
Catherine H. Gebotys:
Current flattening in software and hardware for security applications.
CODES+ISSS 2004: 218-223 |
| 34 | EE | Catherine H. Gebotys:
Low energy security optimization in embedded cryptographic systems.
CODES+ISSS 2004: 224-229 |
| 33 | EE | Peter Marwedel,
Catherine H. Gebotys:
Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches?
CODES+ISSS 2004: 72 |
| 32 | EE | Catherine H. Gebotys:
Design of secure cryptography against the threat of power-attacks in DSP-embedded processors.
ACM Trans. Embedded Comput. Syst. 3(1): 92-113 (2004) |
| 2003 |
|---|
| 31 | EE | Catherine H. Gebotys,
Y. Zhang:
Security wrappers and power analysis for SoC technologies.
CODES+ISSS 2003: 162-167 |
| 30 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
A Framework for Security on NoC Technologies.
ISVLSI 2003: 113-120 |
| 2002 |
|---|
| 29 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor.
CHES 2002: 114-128 |
| 28 | EE | Hiroto Yasuura,
Naofumi Takagi,
Srivaths Ravi,
Michael Torla,
Catherine H. Gebotys:
Special Session: Security on SoC.
ISSS 2002: 192-194 |
| 27 | EE | Catherine H. Gebotys:
Security-Driven Exploration of Cryptography in DSP Cores.
ISSS 2002: 80-85 |
| 26 | EE | Catherine H. Gebotys:
A network flow approach to memory bandwidth utilization in embedded DSP core processors.
IEEE Trans. VLSI Syst. 10(4): 390-398 (2002) |
| 2001 |
|---|
| 25 | EE | Catherine H. Gebotys:
Utilizing Memory Bandwidth in DSP Embedded Processors.
DAC 2001: 347-352 |
| 24 | | Radu Muresan,
Catherine H. Gebotys:
Current consumption dynamics at instruction and program level for a VLIW DSP processor.
ISSS 2001: 130-135 |
| 23 | | Catherine H. Gebotys,
Radu Muresan:
Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model.
VLSI-SOC 2001: 205-216 |
| 2000 |
|---|
| 22 | EE | Catherine H. Gebotys,
Robert J. Gebotys,
S. Wiratunga:
Power minimization derived from architectural-usage of VLIW processors.
DAC 2000: 308-311 |
| 1999 |
|---|
| 21 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Designing for Low Power in Complex Embedded DSP Systems.
HICSS 1999 |
| 20 | EE | Catherine H. Gebotys:
A minimum-cost circulation approach to DSP address-code generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 726-741 (1999) |
| 1998 |
|---|
| 19 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability.
HICSS (3) 1998: 150-156 |
| 18 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors.
ISLPED 1998: 121-123 |
| 1997 |
|---|
| 17 | EE | Catherine H. Gebotys:
Low Energy Memory and Register Allocation Using Network Flow.
DAC 1997: 435-440 |
| 16 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Performance-Power Optimization of Memory Components for Complex Embedded Systems.
HICSS (5) 1997: 152-159 |
| 15 | EE | Catherine H. Gebotys:
DSP address optimization using a minimum cost circulation technique.
ICCAD 1997: 100-103 |
| 14 | EE | Catherine H. Gebotys:
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy.
ISSS 1997: 41- |
| 13 | | Sarita V. Adve,
Doug Burger,
Rudolf Eigenmann,
Alasdair Rawsthorne,
Michael D. Smith,
Catherine H. Gebotys,
Mahmut T. Kandemir,
David J. Lilja,
Alok N. Choudhary,
Jesse Zhixi Fang,
Pen-Chung Yew:
Changing Interaction of Compiler and Architecture.
IEEE Computer 30(12): 51-58 (1997) |
| 1996 |
|---|
| 12 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Power Minimization in Heterogeneous Processing.
HICSS (1) 1996: 330-337 |
| 1995 |
|---|
| 11 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Optimized mapping of video applications to hardware-software for VLSI architectures.
HICSS (1) 1995: 41-48 |
| 10 | EE | Catherine H. Gebotys:
An optimal methodology for synthesis of DSP multichip architectures.
VLSI Signal Processing 11(1-2): 9-19 (1995) |
| 1994 |
|---|
| 9 | | Catherine H. Gebotys,
Robert J. Gebotys:
Application-Specific Architectures for Field-Programmable VLSI Technologies.
HICSS (1) 1994: 124-131 |
| 8 | EE | Catherine H. Gebotys:
An optimization approach to the synthesis of multichip architectures.
IEEE Trans. VLSI Syst. 2(1): 11-20 (1994) |
| 1993 |
|---|
| 7 | EE | Catherine H. Gebotys:
Throughput optimized architectural synthesis.
IEEE Trans. VLSI Syst. 1(3): 254-261 (1993) |
| 6 | EE | Catherine H. Gebotys,
Mohamed I. Elmasry:
Global optimization approach for architectural synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1266-1278 (1993) |
| 1992 |
|---|
| 5 | EE | Catherine H. Gebotys:
Optimal Scheduling and Allocation of Embedded VLSI Chips.
DAC 1992: 116-119 |
| 4 | EE | Catherine H. Gebotys:
Optimal synthesis of multichip architectures.
ICCAD 1992: 238-241 |
| 1991 |
|---|
| 3 | EE | Catherine H. Gebotys,
Mohamed I. Elmasry:
Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis.
DAC 1991: 2-7 |
| 1990 |
|---|
| 2 | | Catherine H. Gebotys,
Mohamed I. Elmasry:
A Global Optimization Approach for Architectural Synthesis.
ICCAD 1990: 258-261 |
| 1988 |
|---|
| 1 | EE | Catherine H. Gebotys,
Mohamed I. Elmasry:
VLSI Design Synthesis with Testability.
DAC 1988: 16-21 |
