| 2008 |
|---|
| 10 | EE | Yi Hsuan Wu,
Yu Ting Liu,
Hsiu-Chi Chang,
Yen-Chin Liao,
Hsie-Chia Chang:
Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints.
ICC 2008: 4496-4500 |
| 9 | EE | Yi-Kai Lin,
Chin-Lung Chen,
Yen-Chin Liao,
Hsie-Chia Chang:
Structured LDPCcodes with low error floor based on PEG tanner graphs.
ISCAS 2008: 1846-1849 |
| 8 | EE | Chih-Hao Liu,
Chien-Ching Lin,
Hsie-Chia Chang,
Chen-Yi Lee,
Yarsun Hsua:
Multi-mode message passing switch networks applied for QC-LDPC decoder.
ISCAS 2008: 752-755 |
| 2007 |
|---|
| 7 | EE | Yen-Chin Liao,
Chien-Ching Lin,
Hsie-Chia Chang,
Chih-Wei Liu:
Self-Compensation Technique for Simplified Belief-Propagation Algorithm.
IEEE Transactions on Signal Processing 55(6-2): 3061-3072 (2007) |
| 2006 |
|---|
| 6 | EE | Hong-An Huang,
Yen-Chin Liao,
Hsie-Chia Chang:
A self-compensation fixed-width booth multiplier and its 128-point FFT applications.
ISCAS 2006 |
| 5 | EE | Chien-Ching Lin,
Y.-H. Shih,
Hsie-Chia Chang,
Chen-Yi Lee:
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. VLSI Syst. 14(4): 426-430 (2006) |
| 2004 |
|---|
| 4 | | Yi-Chen Tseng,
Chien-Ching Lin,
Hsie-Chia Chang,
Chen-Yi Lee:
A power and area efficient multi-mode FEC processor.
ISCAS (2) 2004: 253-256 |
| 3 | | Hsie-Chia Chang,
Chien-Ching Lin,
Tien-Yuan Hsiao,
Jieh-Tsorng Wu,
Ta-Hui Wang:
Multi-level memory systems using error control codes.
ISCAS (2) 2004: 393-396 |
| 2003 |
|---|
| 2 | EE | Hsie-Chia Chang,
Chen-Yi Lee:
A Low-Power Design for Reed-Solomon Decoders.
Journal of Circuits, Systems, and Computers 12(2): 159-170 (2003) |
| 2001 |
|---|
| 1 | EE | Hsie-Chia Chang,
Chen-Yi Lee:
An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm.
ISCAS (2) 2001: 649-652 |
