| 2007 |
|---|
| 7 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Architectural Support for Run-Time Validation of Program Data Properties.
IEEE Trans. VLSI Syst. 15(5): 546-559 (2007) |
| 6 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Murugan Sankaradass,
Niraj K. Jha,
Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.
IEEE Trans. VLSI Syst. 15(6): 699-710 (2007) |
| 2006 |
|---|
| 5 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Architectural support for safe software execution on embedded processors.
CODES+ISSS 2006: 106-111 |
| 4 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Murugan Sankaradass,
Niraj K. Jha,
Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.
DAC 2006: 496-501 |
| 3 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.
IEEE Trans. VLSI Syst. 14(12): 1295-1308 (2006) |
| 2005 |
|---|
| 2 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Enhancing security through hardware-assisted run-time validation of program data properties.
CODES+ISSS 2005: 190-195 |
| 1 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.
DATE 2005: 178-183 |
