Chingwei Yeh

Ching-Wei Yeh

2007
30	EE	Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh: Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. HiPEAC 2007: 105-119
2006
29	EE	De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh: Timing driven power gating. DAC 2006: 121-124
28	EE	Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang: A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. DATE Designers' Forum 2006: 239-243
27	EE	Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang: An 830mW, 586kbps 1024-bit RSA chip design. DATE Designers' Forum 2006: 24-29
26	EE	Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu: Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS 2006
25	EE	Chi-Shong Wang, Chingwei Yeh: Performance-driven technology mapping with MSG partition and selective gate duplication. ACM Trans. Design Autom. Electr. Syst. 11(4): 953-973 (2006)
24	EE	Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh: Power minimization for dynamic PLAs. IEEE Trans. VLSI Syst. 14(6): 616-624 (2006)
2005
23	EE	Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh: Power minimization for dynamic PLAs. ASP-DAC 2005: 1010-1013
22	EE	Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh: A low-power high-SFDR CMOS direct digital frequency synthesizer. ISCAS (2) 2005: 1670-1673
21	EE	Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen: An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. IEEE Trans. Circuits Syst. Video Techn. 15(5): 704-715 (2005)
2004
20		Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh: A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. ICME 2004: 1683-1686
19		Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen: A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. ISCAS (2) 2004: 141-144
18		Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh: Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. ISCAS (2) 2004: 401-404
2001
17	EE	Chingwei Yeh, Yin-Shuin Kang: Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. VLSI Syst. 9(6): 983-986 (2001)
2000
16	EE	Chingwei Yeh, Yin-Shuin Kang: Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. VLSI Syst. 8(5): 629-633 (2000)
1999
15	EE	Ching-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang: Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs. ARVLSI 1999: 155-169
14	EE	Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang: Technnology Mapping for Low Power. ASP-DAC 1999: 145-148
13	EE	Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang: Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. DAC 1999: 62-67
12	EE	Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone: Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. DAC 1999: 68-71
11	EE	Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone: Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) 1999: 246-249
10	EE	Chingwei Yeh, Yin-Shuin Kang: A simulated annealing based method supporting dual supply voltages in standard cell placement. ISCAS (1) 1999: 310-313
9	EE	Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang: A cell selection strategy for low power applications. ISCAS (6) 1999: 416-419
1996
8	EE	Chingwei Yeh, Chi-Shong Wang: On the integration of partitioning and global routing for rectilinear placement problems. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 83-91 (1996)
1995
7	EE	Ching-Wei Yeh: On the acceleration of flow-oriented circuit clustering. IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1305-1308 (1995)
6	EE	Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimization by iterative improvement: an experimental evaluation on two-way partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 145-153 (1995)
5	EE	Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: Circuit clustering using a stochastic flow injection method. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 154-162 (1995)
1994
4	EE	Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel: Block-oriented programmable design with switching network interconnect. IEEE Trans. VLSI Syst. 2(1): 45-53 (1994)
3	EE	Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A general purpose, multiple-way partitioning algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1480-1488 (1994)
1992
2	EE	Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A probabilistic multicommodity-flow solution to circuit clustering problems. ICCAD 1992: 428-431
1991
1	EE	Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A General Purpose Multiple Way Partitioning Algorithm. DAC 1991: 421-426

Coauthor Index

1	S. Ahmed	[4]
2	Chin-Chao Chang	[9] [14]
3	Kuei-Chung Chang	[30]
4	Min-Cheng Chang	[11] [12] [15]
5	Nai-Jen Chang	[27]
6	Shih-Chieh Chang	[11] [12] [23] [24] [29]
7	Yu-Juey Chang	[26]
8	Jia-Wei Chen	[21]
9	Kuan-Hung Chen	[19] [20] [21]
10	Shih-Hsin Chen	[29]
11	Tien-Fu Chen	[19] [30]
12	Chung-Kuan Cheng	[1] [2] [3] [4] [5] [6]
13	Kai-Wen Cheng	[27]
14	De-Shiuan Chiou	[29]
15	Yuan-Hua Chu	[26]
16	Jiun-In Guo	[19] [20] [21]
17	En-Feng Hsu	[27]
18	T. C. Hu	[4]
19	Wen-Ben Jone	[11] [12]
20	Yin-Shuin Kang	[10] [13] [15] [16] [17]
21	Lin-Chi Lee	[28]
22	M. Liddel	[4]
23	Shiang-Jiun Lin	[22]
24	Ting-Ting Y. Lin	[1] [2] [3] [5] [6]
25	Lung-Tien Liu	[4]
26	Shan-Jih Shieh	[13]
27	Shang-Jyh Shieh	[18]
28	Tzyy-Kuen Tien	[23] [24]
29	Chih-Shen Tsai	[23] [24]
30	Chao-Ching Wang	[28]
31	Chi-Shong Wang	[8] [25]
32	Jinn-Shyan Wang	[9] [13] [14] [18] [19] [20] [21] [22] [26] [27] [28]
33	Chang-Ching Yeh	[30]
34	Yuan-Hsun Yeh	[18]

Colors in the list of coauthors