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Kyeong-Sik Min

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2009
10EEJi-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang: New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. ISQED 2009: 459-464
2008
9EEDuk-Hyung Lee, Daejeong Kim, Ho-Jun Song, Kyeong-Sik Min: A Modified Dickson Charge Pump Circuit with High Efficiency and High Output Voltage. IEICE Transactions 91-C(2): 228-231 (2008)
8EEDuk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min: Comparative Study on Leakage Current of Power-Gated SRAMs for 65-nm, 45-nm, 32-nm Technology Nodes. JCP 3(3): 39-47 (2008)
2007
7EEDuk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min: Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs. VLSI Design 2007: 632-637
6EEKyeong-Sik Min, Manh-Dat Vu: An Approach for Numerical Analysis of Differential Equation-Based Feeding Point Modeling of Electromagnetic Devices. IEICE Transactions 90-B(5): 1208-1213 (2007)
5EEO-Sam Kwon, Kyeong-Sik Min: Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications. IEICE Transactions 90-C(7): 1540-1543 (2007)
2006
4EEKyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai: Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs. IEEE Trans. VLSI Syst. 14(4): 430-435 (2006)
2005
3EEKyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai: Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. IEICE Transactions 88-C(4): 760-767 (2005)
2004
2EEKyeong-Sik Min, Young-Hee Kim, Daejeong Kim, Dong Myeong Kim, Jin-Hong Ahn: A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications. ASP-DAC 2004: 288-291
2002
1EEKyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai: CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. ISCAS (5) 2002: 545-548

Coauthor Index

1Jin-Hong Ahn [1] [2]
2Ji-Hye Bong [10]
3H.-Y. Choi [4]
4Hoon-Dae Choi [3]
5Hun-Dae Choi [4]
6Hyun-Young Choi [3]
7Jin-Yong Chung [1]
8Kenichi Inagaki [3]
9Kouichi Kanda [3]
10Sung-Mo Kang [10]
11Hiroshi Kawaguchi [3] [4]
12Daejeong Kim [2] [3] [9]
13Dong Myeong Kim [2]
14Dong Myong Kim [3]
15Young-Hee Kim [1] [2]
16Dong-Kone Kwak [7] [8]
17O-Sam Kwon [5]
18Yong-Jin Kwon [10]
19Duk-Hyung Lee [7] [8] [9]
20Takayasu Sakurai [1] [3] [4]
21Fayez Robert Saliba [3]
22Ho-Jun Song [9]
23Manh-Dat Vu [6]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)