Yuvraj Singh Dhillon

2007
14	EE	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee: Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits CoRR abs/0710.4720: (2007)
13	EE	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee: Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption. J. Low Power Electronics 3(1): 78-95 (2007)
2006
12	EE	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh: Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. IEEE Trans. VLSI Syst. 14(5): 514-524 (2006)
2005
11	EE	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh: Low-power domino circuits using NMOS pull-up on off-critical paths. ASP-DAC 2005: 533-538
10	EE	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee: Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. DATE 2005: 288-293
9	EE	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra: Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. IOLTS 2005: 35-40
8	EE	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh: Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. VLSI Design 2005: 159-164
7	EE	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh: Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. VTS 2005: 298-303
6	EE	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh: Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. IEEE Trans. VLSI Syst. 13(9): 1103-1107 (2005)
5	EE	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh: Pseudo Dual Supply Voltage Domino Logic Design. J. Low Power Electronics 1(2): 145-152 (2005)
2004
4	EE	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh: Sizing CMOS Circuits for Increased Transient Error Tolerance. IOLTS 2004: 11-16
3	EE	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh: Low-power dual Vth pseudo dual Vdd domino circuits. SBCCI 2004: 273-277
2003
2	EE	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee: Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. ICCAD 2003: 693-700
1	EE	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee: An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs. ISVLSI 2003: 173-182

Coauthor Index

1	Abhijit Chatterjee	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
2	Kyu-won Choi	[1]
3	Abdulkadir Utku Diril	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
4	Hsien-Hsin S. Lee	[2]
5	Cecilia Metra	[9]
6	Adit D. Singh	[3] [4] [5] [6] [7] [8] [11] [12]