| |
| 2006 | ||
|---|---|---|
| 6 | EE | Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu: Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. IEEE Trans. VLSI Syst. 14(1): 34-42 (2006) |
| 1991 | ||
| 5 | Viktor K. Prasanna, Yu-Chen Tsai: On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication. IEEE Trans. Computers 40(6): 770-774 (1991) | |
| 1990 | ||
| 4 | EE | V. K. Prasanna Kumar, Yu-Chen Tsai: Mapping dynamic programming onto a linear systolic array. VLSI Signal Processing 1(4): 335-343 (1990) |
| 1989 | ||
| 3 | Viktor K. Prasanna, Yu-Chen Tsai: On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays. IEEE Trans. Computers 38(3): 470-478 (1989) | |
| 2 | Viktor K. Prasanna, Yu-Chen Tsai: Designing Linear Systolic Arrays. J. Parallel Distrib. Comput. 7(3): 441-463 (1989) | |
| 1988 | ||
| 1 | Viktor K. Prasanna, Yu-Chen Tsai: Mapping Two Dimensional Systolic Arrays to One Dimensional Arrays and Applications. ICPP (1) 1988: 39-46 | |
| 1 | Chih-Hsien Hsu | [6] |
| 2 | Shyue-Kung Lu | [6] |
| 3 | Viktor K. Prasanna (V. K. Prasanna Kumar) | [1] [2] [3] [4] [5] |
| 4 | Kuo-Hua Wang | [6] |
| 5 | Cheng-Wen Wu | [6] |