| 2008 |
| 24 | EE | Zhiqiang Cui,
Zhongfeng Wang:
Extended layered decoding of LDPC codes.
ACM Great Lakes Symposium on VLSI 2008: 457-462 |
| 23 | EE | Jiangli Zhu,
Xinmiao Zhang,
Zhongfeng Wang:
Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes.
ICCD 2008: 526-531 |
| 22 | EE | Jinjin He,
Jian Cui,
Lianxing Yang,
Zhongfeng Wang:
A low-complexity high-performance noncoherent receiver for GFSK signals.
ISCAS 2008: 1256-1259 |
| 21 | EE | Jiangli Zhu,
Xinmiao Zhang,
Zhongfeng Wang:
Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes.
ISCAS 2008: 3078-3081 |
| 2007 |
| 20 | EE | Jun Ma,
Alexander Vardy,
Zhongfeng Wang,
Qinqin Chen:
Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes.
ISCAS 2007: 1409-1412 |
| 19 | EE | Qinqin Chen,
Zhongfeng Wang,
Jun Ma:
FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes.
ISCAS 2007: 2100-2103 |
| 18 | EE | Zhiqiang Cui,
Zhongfeng Wang:
Efficient Message Passing Architecture for High Throughput LDPC Decoder.
ISCAS 2007: 917-920 |
| 17 | EE | Zhongfeng Wang,
Zhiqiang Cui:
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes.
IEEE Trans. VLSI Syst. 15(1): 104-114 (2007) |
| 16 | EE | Jun Ma,
Alexander Vardy,
Zhongfeng Wang:
Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes.
IEEE Trans. VLSI Syst. 15(11): 1225-1238 (2007) |
| 15 | EE | Zhongfeng Wang,
Zhiqiang Cui:
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes.
IEEE Trans. VLSI Syst. 15(4): 483-488 (2007) |
| 2006 |
| 14 | EE | Jin Sha,
Ming-Lun Gao,
Zhongjin Zhang,
Li Li,
Zhongfeng Wang:
An FPGA Implementation of Array LDPC Decoder.
APCCAS 2006: 1675-1678 |
| 13 | EE | Zhiqiang Cui,
Zhongfeng Wang:
A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA.
ISCAS 2006 |
| 12 | EE | Zhiqiang Cui,
Zhongfeng Wang:
Area-efficient parallel decoder architecture for high rate QC-LDPC codes.
ISCAS 2006 |
| 11 | EE | Jun Ma,
Alexander Vardy,
Zhongfeng Wang:
Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes.
ISCAS 2006 |
| 10 | EE | Qingwei Li,
Zhongfeng Wang:
Improved k-best sphere decoding algorithms for MIMO systems.
ISCAS 2006 |
| 9 | EE | Jun Ma,
Alexander Vardy,
Zhongfeng Wang:
Reencoder design for soft-decision decoding of an (255, 239) Reed-Solomon code.
ISCAS 2006 |
| 8 | EE | Zhongfeng Wang,
Jun Ma:
High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes.
IEEE Trans. VLSI Syst. 14(9): 937-950 (2006) |
| 2005 |
| 7 | EE | Zhongfeng Wang,
Qing-wei Jia:
Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes.
ISCAS (6) 2005: 5786-5789 |
| 2004 |
| 6 | EE | Zhipei Chi,
Zhongfeng Wang,
Keshab K. Parhi:
On the better protection of short-frame turbo codes.
IEEE Transactions on Communications 52(9): 1435-1439 (2004) |
| 2003 |
| 5 | EE | Zhongfeng Wang,
Yiyan Tang,
Yuke Wang:
Low hardware complexity parallel turbo decoder architecture.
ISCAS (2) 2003: 53-56 |
| 2002 |
| 4 | EE | Zhongfeng Wang,
Zhipei Chi,
Keshab K. Parhi:
Area-efficient high-speed decoding schemes for turbo decoders.
IEEE Trans. VLSI Syst. 10(6): 902-912 (2002) |
| 2001 |
| 3 | EE | Tong Zhang,
Zhongfeng Wang,
Keshab K. Parhi:
On finite precision implementation of low density parity check codes decoder.
ISCAS (4) 2001: 202-205 |
| 2 | EE | Zhongfeng Wang,
Hiroshi Suzuki,
Keshab K. Parhi:
Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders.
VLSI Signal Processing 29(3): 209-221 (2001) |
| 1999 |
| 1 | EE | S. Summerfield,
Zhongfeng Wang,
Keshab K. Parhi:
Area-power-time efficient pipeline-interleaved architectures for wave digital filters.
ISCAS (3) 1999: 343-346 |