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Chi Ta Wu

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2006
2EEChi Ta Wu, Ang-Chih Hsieh, TingTing Hwang: Instruction buffering for nested loops in low-power design. IEEE Trans. VLSI Syst. 14(7): 780-784 (2006)
2002
1EEChi Ta Wu, TingTing Hwang: Instruction buffering for nested loops in low power design. ISCAS (4) 2002: 81-84

Coauthor Index

1Ang-Chih Hsieh [2]
2TingTing Hwang [1] [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)