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Foster F. Dai

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2007
15EEJie Qin, Charles E. Stroud, Foster F. Dai: Noise Figure Measurement Using Mixed-Signal BIST. ISCAS 2007: 2180-2183
14EELing Yuan, Weining Ni, Yin Shi, Foster F. Dai: A 10-bit 2GHz Current-Steering CMOS D/A Converter. ISCAS 2007: 737-740
2006
13EEWeining Ni, Xueyang Geng, Yin Shi, Foster F. Dai: A 12-bit 300 MHz CMOS DAC for high-speed system applications. ISCAS 2006
12EEYuan Yao, Xuefeng Yu, Foster F. Dai, Richard C. Jaeger: A 12-bit current steering DAC for cryogenic applications. ISCAS 2006
11EEOimins Xu, Xueqing Hu, Pens Gao, Jun Yan, Shi Yin, Foster F. Dai, Richard C. Jaeger: A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver. ISCAS 2006
10EECharles E. Stroud, Dayu Yang, Foster F. Dai: Analog frequency response measurement in mixed-signal systems. ISCAS 2006
9EEFoster F. Dai, Charles E. Stroud, Dayu Yang: Automatic linearity and frequency response tests with built-in pattern generator and analyzer. IEEE Trans. VLSI Syst. 14(6): 561-572 (2006)
2005
8EEYuan Yao, Yin Shi, Foster F. Dai: A novel low-power input-independent MOS AC/DC charge pump. ISCAS (1) 2005: 380-383
7EEVasanth Kakani, Foster F. Dai, Richard C. Jaeger: An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks. ISCAS (2) 2005: 1178-1181
6EEDayu Yang, Foster F. Dai, Charles E. Stroud: Built-in self-test for automatic analog frequency response measurement. ISCAS (3) 2005: 2208-2211
5EEXuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu: 2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer. ISCAS (5) 2005: 4397-4400
4EEFoster F. Dai, Shengfang Wei, Richard D. Jaeger: Integrated blind electronic equalizer for fiber dispersion compensation. ISCAS (6) 2005: 5750-5753
2004
3 Malinky Ghosh, Lakshmi S. J. Chimakurthy, Foster F. Dai, Richard C. Jaeger: A novel DDS architecture using nonlinear ROM addressing with improved compression ratio and quantisation noise. ISCAS (2) 2004: 705-708
2 Vasanth Kakani, Foster F. Dai, Richard C. Jaeger: Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits. ISCAS (2) 2004: 869-872
1EEFoster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi: Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. ITC 2004: 271-280

Coauthor Index

1Lakshmi S. J. Chimakurthy [3]
2Pens Gao [11]
3Xueyang Geng [13]
4Malinky Ghosh [3]
5Xueqing Hu [11]
6Richard C. Jaeger [2] [3] [7] [11] [12]
7Richard D. Jaeger [4]
8Vasanth Kakani [2] [7]
9Weining Ni [13] [14]
10Shuying Qi [1]
11Jie Qin [15]
12Yin Shi [5] [8] [13] [14]
13Charles E. Stroud [1] [6] [9] [10] [15]
14Shengfang Wei [4]
15Oimins Xu [11]
16Jun Yan [11]
17Dayu Yang [1] [6] [9] [10]
18Yuan Yao [8] [12]
19Shi Yin [11]
20Xuefeng Yu [5] [12]
21Ling Yuan [14]
22Ronghua Zhu [5]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)