Foster F. Dai

2007
15	EE	Jie Qin, Charles E. Stroud, Foster F. Dai: Noise Figure Measurement Using Mixed-Signal BIST. ISCAS 2007: 2180-2183
14	EE	Ling Yuan, Weining Ni, Yin Shi, Foster F. Dai: A 10-bit 2GHz Current-Steering CMOS D/A Converter. ISCAS 2007: 737-740
2006
13	EE	Weining Ni, Xueyang Geng, Yin Shi, Foster F. Dai: A 12-bit 300 MHz CMOS DAC for high-speed system applications. ISCAS 2006
12	EE	Yuan Yao, Xuefeng Yu, Foster F. Dai, Richard C. Jaeger: A 12-bit current steering DAC for cryogenic applications. ISCAS 2006
11	EE	Oimins Xu, Xueqing Hu, Pens Gao, Jun Yan, Shi Yin, Foster F. Dai, Richard C. Jaeger: A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver. ISCAS 2006
10	EE	Charles E. Stroud, Dayu Yang, Foster F. Dai: Analog frequency response measurement in mixed-signal systems. ISCAS 2006
9	EE	Foster F. Dai, Charles E. Stroud, Dayu Yang: Automatic linearity and frequency response tests with built-in pattern generator and analyzer. IEEE Trans. VLSI Syst. 14(6): 561-572 (2006)
2005
8	EE	Yuan Yao, Yin Shi, Foster F. Dai: A novel low-power input-independent MOS AC/DC charge pump. ISCAS (1) 2005: 380-383
7	EE	Vasanth Kakani, Foster F. Dai, Richard C. Jaeger: An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks. ISCAS (2) 2005: 1178-1181
6	EE	Dayu Yang, Foster F. Dai, Charles E. Stroud: Built-in self-test for automatic analog frequency response measurement. ISCAS (3) 2005: 2208-2211
5	EE	Xuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu: 2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer. ISCAS (5) 2005: 4397-4400
4	EE	Foster F. Dai, Shengfang Wei, Richard D. Jaeger: Integrated blind electronic equalizer for fiber dispersion compensation. ISCAS (6) 2005: 5750-5753
2004
3		Malinky Ghosh, Lakshmi S. J. Chimakurthy, Foster F. Dai, Richard C. Jaeger: A novel DDS architecture using nonlinear ROM addressing with improved compression ratio and quantisation noise. ISCAS (2) 2004: 705-708
2		Vasanth Kakani, Foster F. Dai, Richard C. Jaeger: Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits. ISCAS (2) 2004: 869-872
1	EE	Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi: Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. ITC 2004: 271-280

Coauthor Index

1	Lakshmi S. J. Chimakurthy	[3]
2	Pens Gao	[11]
3	Xueyang Geng	[13]
4	Malinky Ghosh	[3]
5	Xueqing Hu	[11]
6	Richard C. Jaeger	[2] [3] [7] [11] [12]
7	Richard D. Jaeger	[4]
8	Vasanth Kakani	[2] [7]
9	Weining Ni	[13] [14]
10	Shuying Qi	[1]
11	Jie Qin	[15]
12	Yin Shi	[5] [8] [13] [14]
13	Charles E. Stroud	[1] [6] [9] [10] [15]
14	Shengfang Wei	[4]
15	Oimins Xu	[11]
16	Jun Yan	[11]
17	Dayu Yang	[1] [6] [9] [10]
18	Yuan Yao	[8] [12]
19	Shi Yin	[11]
20	Xuefeng Yu	[5] [12]
21	Ling Yuan	[14]
22	Ronghua Zhu	[5]

Colors in the list of coauthors