Per Larsson-Edefors

2008
30	EE	Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors: Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. ISQED 2008: 663-669
29	EE	Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson: Noise Interaction Between Power Distribution Grids and Substrate. ISQED 2008: 84-89
2007
28	EE	Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis: High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. DSD 2007: 249-256
27	EE	Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ICSAMOS 2007: 18-25
26	EE	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ISQED 2007: 185-191
25	EE	Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson: Overdrive Power-Gating Techniques for Total Power Minimization. ISVLSI 2007: 125-132
24	EE	Magnus Själander, Per Larsson-Edefors, Magnus Björk: A Flexible Datapath Interconnect for Embedded Applications. ISVLSI 2007: 15-20
2006
23	EE	Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, D. Johansson, M. Scholin: Multiplier reduction tree with logarithmic logic depth and regular connectivity. ISCAS 2006
22	EE	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ISQED 2006: 557-563
21	EE	Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert: Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. VLSI Syst. 14(4): 370-379 (2006)
2005
20	EE	Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors: Accounting for the skin effect during repeater insertion. ACM Great Lakes Symposium on VLSI 2005: 32-37
19	EE	Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson: A low-leakage twin-precision multiplier using reconfigurable power gating. ISCAS (2) 2005: 1654-1657
2004
18	EE	Magnus Själander, Henrik Eriksson, Per Larsson-Edefors: An Efficient Twin-Precision Multiplier. ICCD 2004: 30-33
17		Henrik Eriksson, Per Larsson-Edefors: Glitch-conscious low-power design of arithmetic circuits. ISCAS (2) 2004: 281-284
16		Henrik Eriksson, Per Larsson-Edefors: Dynamic pass-transistor dot operators for efficient parallel-prefix adders. ISCAS (2) 2004: 461-464
15		Mindaugas Drazdziulis, Per Larsson-Edefors: Evaluation of power cut-off techniques in the presence of gate leakage. ISCAS (2) 2004: 745-748
14	EE	Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors: On Skin Effect in On-Chip Interconnects. PATMOS 2004: 463-470
13	EE	Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson: Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. PATMOS 2004: 869-878
12	EE	Dainius Ciuplys, Per Larsson-Edefors: On Maximum Current Estimation in CMOS Digital Circuits. VLSI Design 2004: 658-661
2003
11		Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors: DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. Applied Informatics 2003: 767-772
10	EE	Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors: A Mixed-Mode Delay-Locked-Loop Architecture. ICCD 2003: 261-263
9	EE	Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson: Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI 2003: 225-230
2001
8	EE	Daniel Eckerbert, Per Larsson-Edefors: Interconnect-Driven Short-Circuit Power Modeling. DSD 2001: 414-421
7	EE	Henrik Eriksson, Per Larsson-Edefors, William P. Marnane: A regular parallel multiplier which utilizes multiple carry-propagate adders. ISCAS (4) 2001: 166-169
6	EE	Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour: A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. ISCAS (4) 2001: 84-87
5	EE	Daniel Eckerbert, Per Larsson-Edefors: Cycle-true leakage current modeling for CMOS gates. ISCAS (5) 2001: 507-510
2000
4	EE	Henrik Eriksson, Per Larsson-Edefors: Impact of Voltage Scaling on Glitch Power Consumption. PATMOS 2000: 139-148
1998
3	EE	Per Larsson-Edefors: A Miniature Serial-Data SIMD Architecture. EUROMICRO 1998: 10341-10344
2	EE	Atila Alvandpour, Per Larsson-Edefors, Christer Svensson: Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. ISLPED 1998: 245-249
1996
1	EE	Per Larsson-Edefors: Technology mapping onto very-high-speed standard CMOS hardware. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1137-1144 (1996)

Coauthor Index

1	Atila Alvandpour	[2] [6]
2	Daniel A. Andersson	[14] [20] [29] [30]
3	Lars Bengtsson	[11] [13] [22] [26]
4	Magnus Björk	[24] [27]
5	Dainius Ciuplys	[12]
6	Minh Quang Do	[11] [13] [22] [26] [28]
7	Mindaugas Drazdziulis	[15] [19] [22] [25] [26] [28]
8	Daniel Eckerbert	[5] [8] [9] [10] [21]
9	Henrik Eriksson	[4] [6] [7] [9] [16] [17] [18] [19] [21] [23]
10	Kjell O. Jeppson	[29]
11	D. Johansson	[23]
12	Simon Kristiansson	[29]
13	William P. Marnane	[7]
14	M. Scholin	[23]
15	Mary Sheeran	[23]
16	Magnus Själander	[18] [19] [23] [24] [27]
17	Per Stenström	[27]
18	Christer Svensson	[2]
19	Lars J. Svensson	[9] [10] [14] [20] [25] [27] [29] [30]
20	Martin Thuresson	[27]

Colors in the list of coauthors