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Daniel Eckerbert

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2006
5EEHenrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert: Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. VLSI Syst. 14(4): 370-379 (2006)
2003
4EEDaniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors: A Mixed-Mode Delay-Locked-Loop Architecture. ICCD 2003: 261-263
3EEPer Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson: Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI 2003: 225-230
2001
2EEDaniel Eckerbert, Per Larsson-Edefors: Interconnect-Driven Short-Circuit Power Modeling. DSD 2001: 414-421
1EEDaniel Eckerbert, Per Larsson-Edefors: Cycle-true leakage current modeling for CMOS gates. ISCAS (5) 2001: 507-510

Coauthor Index

1Henrik Eriksson [3] [5]
2Per Larsson-Edefors [1] [2] [3] [4] [5]
3Lars J. Svensson [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)