| |
| 2006 | ||
|---|---|---|
| 5 | EE | Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert: Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. IEEE Trans. VLSI Syst. 14(4): 370-379 (2006) |
| 2003 | ||
| 4 | EE | Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors: A Mixed-Mode Delay-Locked-Loop Architecture. ICCD 2003: 261-263 |
| 3 | EE | Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson: Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ISVLSI 2003: 225-230 |
| 2001 | ||
| 2 | EE | Daniel Eckerbert, Per Larsson-Edefors: Interconnect-Driven Short-Circuit Power Modeling. DSD 2001: 414-421 |
| 1 | EE | Daniel Eckerbert, Per Larsson-Edefors: Cycle-true leakage current modeling for CMOS gates. ISCAS (5) 2001: 507-510 |
| 1 | Henrik Eriksson | [3] [5] |
| 2 | Per Larsson-Edefors | [1] [2] [3] [4] [5] |
| 3 | Lars J. Svensson | [3] [4] |