2009 |
17 | EE | Jason Cong,
Karthik Gururaj,
Bin Liu,
Chunyue Liu,
Yi Zou,
Zhiru Zhang,
Sheng Zhou:
Revisiting bitwidth optimizations.
FPGA 2009: 278 |
2008 |
16 | EE | Cheng-Tao Hsieh,
Jason Cong,
Zhiru Zhang,
Shih-Chieh Chang:
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.
ASP-DAC 2008: 10-15 |
15 | EE | Wei Jiang,
Zhiru Zhang,
Miodrag Potkonjak,
Jason Cong:
Scheduling with integer time budgeting for low-power optimization.
ASP-DAC 2008: 22-27 |
2007 |
14 | EE | Deming Chen,
Jason Cong,
Yiping Fan,
Zhiru Zhang:
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs.
ASP-DAC 2007: 529-534 |
2006 |
13 | EE | Jason Cong,
Zhiru Zhang:
An efficient and versatile scheduling algorithm based on SDC formulation.
DAC 2006: 433-438 |
12 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Wei Jiang,
Zhiru Zhang:
Behavior and communication co-optimization for systems with sequential communication media.
DAC 2006: 675-678 |
11 | EE | Jason Cong,
Guoling Han,
Zhiru Zhang:
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors.
IEEE Trans. VLSI Syst. 14(9): 986-997 (2006) |
2005 |
10 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Yizhou Lin,
Junjuan Xu,
Zhiru Zhang,
Xu Cheng:
Bitwidth-aware scheduling and binding in high-level synthesis.
ASP-DAC 2005: 856-861 |
9 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Ashok Jagannathan,
Glenn Reinman,
Zhiru Zhang:
Instruction set extension with shadow registers for configurable processors.
FPGA 2005: 99-106 |
8 | | Jason Cong,
Guoling Han,
Zhiru Zhang:
Architecture and compilation for data bandwidth improvement in configurable embedded processors.
ICCAD 2005: 263-270 |
2004 |
7 | EE | Jason Cong,
Yiping Fan,
Zhiru Zhang:
Architecture-level synthesis for automatic interconnect pipelining.
DAC 2004: 602-607 |
6 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Zhiru Zhang:
Application-specific instruction generation for configurable processor architectures.
FPGA 2004: 183-189 |
5 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Xun Yang,
Zhiru Zhang:
Architecture and synthesis for on-chip multicycle communication.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 550-564 (2004) |
2003 |
4 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Xun Yang,
Zhiru Zhang:
Architecture and synthesis for multi-cycle on-chip communication.
CODES+ISSS 2003: 77-78 |
3 | EE | Zhiru Zhang,
Yiping Fan,
Miodrag Potkonjak,
Jason Cong:
Gradual Relaxation Techniques with Applications to Behavioral Synthesis.
ICCAD 2003: 529-535 |
2 | EE | Jason Cong,
Yiping Fan,
Guoling Han,
Xun Yang,
Zhiru Zhang:
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication.
ICCAD 2003: 536-543 |
1 | EE | Jason Cong,
Yiping Fan,
Xun Yang,
Zhiru Zhang:
Architecture and synthesis for multi-cycle communication.
ISPD 2003: 190-196 |