P. Glenn Gulak

2008
30	EE	Mahdi Shabany, P. Glenn Gulak: The application of lattice-reduction to the K-Best algorithm for near-optimal MIMO detection. ISCAS 2008: 316-319
29	EE	Mahdi Shabany, P. Glenn Gulak: Scalable VLSI architecture for K-best lattice decoders. ISCAS 2008: 940-943
2007
28	EE	Mahdi Shabany, P. Glenn Gulak: Application of Sequential Monte Carlo to M-QAM Schemes in the Presence of Nonlinear Solid-State Power Amplifiers. ISCAS 2007: 2295-2298
27	EE	Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak: Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding. IEEE Trans. VLSI Syst. 15(3): 309-318 (2007)
2006
26	EE	Mahdi Shabany, P. Glenn Gulak: An efficient architecture for distributed resampling for high-speed particle filtering. ISCAS 2006
25	EE	Mahdi Shabany, P. Glenn Gulak: VLSI implementation of a sequential Monte Carlo receiver. ISCAS 2006
24	EE	Y. Eslami, Ali Sheikholeslami, P. Glenn Gulak, S. Masui, K. Mukaida: An area-efficient universal cryptography processor for smart cards. IEEE Trans. VLSI Syst. 14(1): 43-56 (2006)
23	EE	Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak: Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Transactions on Communications 54(6): 1143 (2006)
22	EE	Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak: Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Transactions on Communications 54(7): 1224-1234 (2006)
2005
21		David Gnaedig, Emmanuel Boutillon, Michel Jézéquel, Vincent C. Gaudet, P. Glenn Gulak: On Multiple Slice Turbo Codes. Annales des Télécommunications 60(1-2): 79-102 (2005)
20	EE	Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak: Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders. VLSI Signal Processing 39(1-2): 93-111 (2005)
2004
19	EE	Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak: An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding. FCCM 2004: 310-311
1998
18	EE	P. Glenn Gulak: A Review of Multiple-Valued Memory Technology. ISMVL 1998: 222-231
17	EE	Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak: Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic. ISMVL 1998: 264-269
16	EE	Kerry S. Lowe, P. Glenn Gulak: A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 419-434 (1998)
15	EE	Vincent C. Gaudet, P. Glenn Gulak: Implementation Issues for High-Bandwidth Field-Programmable Analog Arrays. Journal of Circuits, Systems, and Computers 8(5-6): 541-558 (1998)
1997
14	EE	Kenneth J. Schultz, P. Glenn Gulak: Authors' reply to "A note on architectures for large-capacity CAMs". Integration 22(1-2): 173-176 (1997)
1996
13	EE	Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu: A Multiple-Valued Ferroelectric Content-Addressable Memory. ISMVL 1996: 74-79
12	EE	Kenneth J. Schultz, P. Glenn Gulak: Multicast contention resolution with single-cycle windowing using content addressable FIFO's. IEEE/ACM Trans. Netw. 4(5): 731-742 (1996)
1995
11	EE	Paul Chow, P. Glenn Gulak, Paul Chow: A Field-Programmable Mixed-Analog-Digital Array. FPGA 1995: 104-109
1994
10		Gennady Feygin, P. Glenn Gulak, Paul Chow: Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference 1994: 254-263
9	EE	Kerry S. Lowe, P. Glenn Gulak: A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits. EURO-DAC 1994: 42-47
8		Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manage. 30(6): 805-816 (1994)
1993
7		Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference 1993: 118-127
6	EE	Kerry S. Lowe, P. Glenn Gulak: Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits. ICCAD 1993: 216-219
5		Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton: A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948
4		Kenneth J. Schultz, P. Glenn Gulak: A Logic-enhanced Memory for Digital Data Recovery Circuits. ISCAS 1993: 2007-2010
1992
3		Edward K. F. Lee, P. Glenn Gulak: Dynamic Current-Mode Multi-Valued MOS Memory with Error Correction. ISMVL 1992: 208-215
1987
2		Howard C. Card, P. Glenn Gulak, Robert D. McLeod, Werner Pries: (lambda, T) Complexity Measures for VLSI Computations in Constant Chip Area. IEEE Trans. Computers 36(1): 112-117 (1987)
1986
1		Gregory E. Bridges, Werner Pries, Robert D. McLeod, M. Yunik, P. Glenn Gulak, Howard C. Card: Dual Systolic Architectures for VLSI Digital Signal Processing Systems. IEEE Trans. Computers 35(10): 916-923 (1986)

Coauthor Index

1	Emmanuel Boutillon	[21]
2	Gregory E. Bridges	[1]
3	Howard C. Card	[1] [2]
4	John Chappel	[5]
5	Paul Chow	[5] [7] [8] [10] [11]
6	Y. Eslami	[24]
7	Gennady Feygin	[5] [7] [8] [10]
8	Vincent C. Gaudet	[15] [21]
9	David Gnaedig	[21]
10	Grant Goodes	[5]
11	Warren J. Gross	[19] [20] [22] [23] [27]
12	Oswin Hall	[5]
13	Takahiro Hanyu	[13]
14	Michel Jézéquel	[21]
15	Ralf Koetter (Ralf Kötter)	[20] [22] [23]
16	Frank R. Kschischang	[19] [20] [22] [23] [27]
17	Edward K. F. Lee	[3]
18	Kerry S. Lowe	[6] [9] [16]
19	S. Masui	[24]
20	Robert D. McLeod	[1] [2]
21	K. Mukaida	[24]
22	Werner Pries	[1] [2]
23	Ahmad Sayes	[5]
24	Kenneth J. Schultz	[4] [12] [14]
25	Mahdi Shabany	[25] [26] [28] [29] [30]
26	Ali Sheikholeslami	[13] [17] [24]
27	Satwant Singh	[5]
28	Michael B. Smith	[5]
29	Steven J. E. Wilton	[5]
30	R. Yoshimura	[17]
31	M. Yunik	[1]

Colors in the list of coauthors