| 2007 |
|---|
| 15 | EE | Hyunchul Shin,
Changhee Lee:
Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits.
IEICE Transactions 90-B(7): 1826-1834 (2007) |
| 14 | EE | Jeongae Park,
Misun Yoon,
Hyunchul Shin:
Efficient Motion Estimation for H.264 Codec by Using Effective Scan Ordering.
IEICE Transactions 90-B(7): 1839-1843 (2007) |
| 2006 |
|---|
| 13 | EE | Hyunchul Shin,
Jin-Aeon Lee,
Lee-Sup Kim:
A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth.
IEEE Trans. VLSI Syst. 14(3): 254-267 (2006) |
| 2003 |
|---|
| 12 | EE | Inho Lee,
Joung-Youn Kim,
Yeon-Ho Im,
Yunseok Choi,
Hyunchul Shin,
Chang-Young Han,
Donghyun Kim,
Hyoungjoon Park,
Young-Il Seo,
Kyusik Chung,
Chang-Hyo Yu,
Kanghyup Chun,
Lee-Sup Kim:
A hardware-like high-level language based environment for 3D graphics architecture exploration.
ISCAS (2) 2003: 512-515 |
| 2001 |
|---|
| 11 | EE | Hyunchul Shin,
Jin-Aeon Lee,
Lee-Sup Kim:
A hardware cost minimized fast Phong shader.
IEEE Trans. VLSI Syst. 9(2): 297-304 (2001) |
| 1998 |
|---|
| 10 | | Wonjong Kim,
Hyunchul Shin:
Hierarchical LVS Based on Hierarchy Rebuilding.
ASP-DAC 1998: 379-384 |
| 1996 |
|---|
| 9 | EE | Chunghee Kim,
Hyunchul Shin:
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 560-568 (1996) |
| 1995 |
|---|
| 8 | EE | Chunghee Kim,
Hyunchul Shin,
Young-Uk Yu:
Performance-driven circuit partitioning for prototyping by using multiple FPGA chips.
ASP-DAC 1995 |
| 7 | EE | Hyunchul Shin,
Chunghee Kim:
Performance-oriented technology mapping for LUT-based FPGA's.
IEEE Trans. VLSI Syst. 3(2): 323-327 (1995) |
| 1993 |
|---|
| 6 | EE | Hyunchul Shin,
Chunghee Kim,
Wonjong Kim,
Myoungsub Oh,
Kwangjoon Rhee,
Seogyun Choi,
Heasoo Chung:
A combined hierarchical placement algorithm.
ICCAD 1993: 164-169 |
| 5 | EE | Hyunchul Shin,
Chunghee Kim:
A simple yet effective technique for partitioning.
IEEE Trans. VLSI Syst. 1(3): 380-386 (1993) |
| 1992 |
|---|
| 4 | EE | Wonjong Kim,
Joohack Lee,
Hyunchul Shin:
A New Hierarchical Layout Compactor Using Simplified Graph Models.
DAC 1992: 323-326 |
| 1990 |
|---|
| 3 | EE | Hyunchul Shin,
Alberto L. Sangiovanni-Vincentelli,
Carlo H. Séquin:
'Zone-refining' techniques for IC layout compaction.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 167-179 (1990) |
| 1987 |
|---|
| 2 | EE | Hyunchul Shin,
Alberto L. Sangiovanni-Vincentelli:
A Detailed Router Based on Incremental Routing Modifications: Mighty.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 942-955 (1987) |
| 1986 |
|---|
| 1 | EE | Hyunchul Shin,
Alberto L. Sangiovanni-Vincentelli,
Carlo H. Séquin:
Two-dimensional compaction by ``zone refining''.
DAC 1986: 115-122 |
