2009 |
20 | EE | Suresh Srinivasan,
Sanu Mathew,
Vasantha Erraguntla,
Ram Krishnamurthy:
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS.
VLSI Design 2009: 301-306 |
2008 |
19 | EE | Himanshu Kaul,
Jae-sun Seo,
Mark Anders,
Dennis Sylvester,
Ram Krishnamurthy:
A robust alternate repeater technique for high performance busses in the multi-core era.
ISCAS 2008: 372-375 |
18 | EE | Rajaraman Ramanarayanan,
Sanu Mathew,
Vasantha Erraguntla,
Ram Krishnamurthy,
Shay Gueron:
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.
VLSI Design 2008: 273-278 |
2007 |
17 | EE | Jae-sun Seo,
Dennis Sylvester,
David Blaauw,
Himanshu Kaul,
Ram Krishnamurthy:
A robust edge encoding technique for energy-efficient multi-cycle interconnect.
ISLPED 2007: 68-73 |
2006 |
16 | EE | Chris H. Kim,
Kaushik Roy,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. VLSI Syst. 14(6): 646-649 (2006) |
2005 |
15 | EE | David Harris,
Ram Krishnamurthy,
Mark Anders,
Sanu Mathew,
Steven Hsu:
An Improved Unified Scalable Radix-2 Montgomery Multiplier.
IEEE Symposium on Computer Arithmetic 2005: 172-178 |
14 | EE | Chris H. Kim,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar,
Kaushik Roy:
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems.
IOLTS 2005: 100-105 |
13 | EE | Steven Hsu,
Amit Agarwal,
Kaushik Roy,
Ram Krishnamurthy,
Shekhar Y. Borkar:
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.
ISLPED 2005: 103-106 |
12 | EE | Himanshu Kaul,
Dennis Sylvester,
Mark Anders,
Ram Krishnamurthy:
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.
IEEE Trans. VLSI Syst. 13(11): 1225-1238 (2005) |
11 | EE | Vojin G. Oklobdzija,
Bart R. Zeydel,
Hoang Q. Dao,
Sanu Mathew,
Ram Krishnamurthy:
Comparison of high-performance VLSI adders in the energy-delay space.
IEEE Trans. VLSI Syst. 13(6): 754-758 (2005) |
10 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies.
Microelectronics Journal 36(9): 801-809 (2005) |
2004 |
9 | EE | Himanshu Kaul,
Dennis Sylvester,
Mark Anders,
Ram Krishnamurthy:
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses.
ISLPED 2004: 194-199 |
8 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.
ISLPED 2004: 248-251 |
7 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.
ISQED 2004: 415-420 |
2003 |
6 | EE | Vojin G. Oklobdzija,
Bart R. Zeydel,
Hoang Q. Dao,
Sanu Mathew,
Ram Krishnamurthy:
Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.
IEEE Symposium on Computer Arithmetic 2003: 272-279 |
5 | EE | Vojin G. Oklobdzija,
Ram Krishnamurthy:
Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs.
IEEE Symposium on Computer Arithmetic 2003: 280 |
4 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar:
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.
ISLPED 2003: 122-127 |
2002 |
3 | EE | Steven Hsu,
Shih-Lien Lu,
Shih-Chang Lai,
Ram Krishnamurthy,
Konrad Lai:
Dynamic addressing memory arrays with physical locality.
MICRO 2002: 161-170 |
2001 |
2 | EE | Ram Krishnamurthy,
Mark Anders,
K. Soumyanath,
Shekhar Borkar:
Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits.
ACM Great Lakes Symposium on VLSI 2001: 43-44 |
1 | EE | Atila Alvandpour,
Ram Krishnamurthy,
K. Soumyanath,
Shekhar Borkar:
A low-leakage dynamic multi-ported register file in 0.13mm CMOS.
ISLPED 2001: 68-71 |