dblp.uni-trier.dewww.uni-trier.de

Giuseppe Cocorullo

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
23EEFabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. PATMOS 2008: 277-286
22EEAndrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo: Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. PATMOS 2008: 318-327
21EEPaolo Zicari, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: A matrix product accelerator for field programmable systems on chip. Microprocessors and Microsystems - Embedded Hardware Design 32(2): 53-67 (2008)
2007
20EEPasquale Corsonello, Stefania Perri, G. Staino, Marco Lanuzza, Giuseppe Cocorullo: Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD 2007: 383-389
19EEAndrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo: Settling Time Minimization of Operational Amplifiers. PATMOS 2007: 107-116
2006
18EEFabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: Leakage energy reduction techniques in deep submicron cache memories: a comparative study. ISCAS 2006
17EEAndrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo: A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. PATMOS 2006: 311-318
16EEAndrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo: Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. PATMOS 2006: 524-531
15EEPasquale Corsonello, Stefania Perri, G. Staino, Marco Lanuzza, Giuseppe Cocorullo: Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Techn. 16(1): 114-128 (2006)
14EEFabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. IEEE Trans. VLSI Syst. 14(11): 1238-1249 (2006)
2005
13EEGregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo: Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. PATMOS 2005: 329-336
12EEStefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: Fast Low-Power 64-Bit Modular Hybrid Adder. PATMOS 2005: 609-617
11EEPasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo: Microprocessor-based FPGA implementation of SPIHT image compression subsystems. Microprocessors and Microsystems 29(6): 299-305 (2005)
10EEStefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo: A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocessors and Microsystems 29(8-9): 381-391 (2005)
2004
9EEStefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo: Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. VLSI Syst. 12(9): 995-999 (2004)
2003
8EEPasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo: Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. FPL 2003: 661-669
7EEStefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: A high-speed energy-efficient 64-bit reconfigurable binary adder. IEEE Trans. VLSI Syst. 11(5): 939-943 (2003)
2002
6EEGregorio Cappuccino, Giuseppe Cocorullo: Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. PATMOS 2002: 438-447
5EEStefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: VLSI circuits for low-power high-speed asynchronous addition. IEEE Trans. VLSI Syst. 10(5): 608-613 (2002)
2001
4EEGregorio Cappuccino, Giuseppe Cocorullo: CMOS sizing rule for high performance long interconnects. DATE 2001: 817
2000
3EEStefania Perri, Pasquale Corsonello, Giuseppe Cocorullo: Designing High-Speed Asynchronous Pipelines. EUROMICRO 2000: 1394-1399
2EEPasquale Corsonello, Stefania Perri, Giuseppe Cocorullo: VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. PATMOS 2000: 195-204
1999
1EEGregorio Cappuccino, Giuseppe Cocorullo: A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines. EUROMICRO 1999: 1204-1208

Coauthor Index

1Francesco A. Amoroso [22]
2Gregorio Cappuccino [1] [4] [6] [13] [16] [17] [19] [22]
3Pasquale Corsonello [2] [3] [5] [7] [8] [9] [10] [11] [12] [14] [15] [18] [20] [21] [23]
4Fabio Frustaci [14] [18] [23]
5Maria Antonia Iachino [8] [9]
6Marco Lanuzza [9] [10] [15] [20]
7Stefania Perri [2] [3] [5] [7] [8] [9] [10] [11] [12] [14] [15] [18] [20] [21] [23]
8Andrea Pugliese [13] [16] [17] [19] [22]
9G. Staino [15] [20]
10Paolo Zicari [11] [21]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)