2008 |
23 | EE | Fabio Frustaci,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.
PATMOS 2008: 277-286 |
22 | EE | Andrea Pugliese,
Francesco A. Amoroso,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.
PATMOS 2008: 318-327 |
21 | EE | Paolo Zicari,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
A matrix product accelerator for field programmable systems on chip.
Microprocessors and Microsystems - Embedded Hardware Design 32(2): 53-67 (2008) |
2007 |
20 | EE | Pasquale Corsonello,
Stefania Perri,
G. Staino,
Marco Lanuzza,
Giuseppe Cocorullo:
Design and Implementation of a 90nm Low bit-rate Image Compression Core.
DSD 2007: 383-389 |
19 | EE | Andrea Pugliese,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Settling Time Minimization of Operational Amplifiers.
PATMOS 2007: 107-116 |
2006 |
18 | EE | Fabio Frustaci,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
Leakage energy reduction techniques in deep submicron cache memories: a comparative study.
ISCAS 2006 |
17 | EE | Andrea Pugliese,
Gregorio Cappuccino,
Giuseppe Cocorullo:
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.
PATMOS 2006: 311-318 |
16 | EE | Andrea Pugliese,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.
PATMOS 2006: 524-531 |
15 | EE | Pasquale Corsonello,
Stefania Perri,
G. Staino,
Marco Lanuzza,
Giuseppe Cocorullo:
Low bit rate image compression core for onboard space applications.
IEEE Trans. Circuits Syst. Video Techn. 16(1): 114-128 (2006) |
14 | EE | Fabio Frustaci,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.
IEEE Trans. VLSI Syst. 14(11): 1238-1249 (2006) |
2005 |
13 | EE | Gregorio Cappuccino,
Andrea Pugliese,
Giuseppe Cocorullo:
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
PATMOS 2005: 329-336 |
12 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
Fast Low-Power 64-Bit Modular Hybrid Adder.
PATMOS 2005: 609-617 |
11 | EE | Pasquale Corsonello,
Stefania Perri,
Paolo Zicari,
Giuseppe Cocorullo:
Microprocessor-based FPGA implementation of SPIHT image compression subsystems.
Microprocessors and Microsystems 29(6): 299-305 (2005) |
10 | EE | Stefania Perri,
Marco Lanuzza,
Pasquale Corsonello,
Giuseppe Cocorullo:
A high-performance fully reconfigurable FPGA-based 2D convolution processor.
Microprocessors and Microsystems 29(8-9): 381-391 (2005) |
2004 |
9 | EE | Stefania Perri,
Pasquale Corsonello,
Maria Antonia Iachino,
Marco Lanuzza,
Giuseppe Cocorullo:
Variable precision arithmetic circuits for FPGA-based multimedia processors.
IEEE Trans. VLSI Syst. 12(9): 995-999 (2004) |
2003 |
8 | EE | Pasquale Corsonello,
Stefania Perri,
Maria Antonia Iachino,
Giuseppe Cocorullo:
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems.
FPL 2003: 661-669 |
7 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
A high-speed energy-efficient 64-bit reconfigurable binary adder.
IEEE Trans. VLSI Syst. 11(5): 939-943 (2003) |
2002 |
6 | EE | Gregorio Cappuccino,
Giuseppe Cocorullo:
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.
PATMOS 2002: 438-447 |
5 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
VLSI circuits for low-power high-speed asynchronous addition.
IEEE Trans. VLSI Syst. 10(5): 608-613 (2002) |
2001 |
4 | EE | Gregorio Cappuccino,
Giuseppe Cocorullo:
CMOS sizing rule for high performance long interconnects.
DATE 2001: 817 |
2000 |
3 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
Designing High-Speed Asynchronous Pipelines.
EUROMICRO 2000: 1394-1399 |
2 | EE | Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.
PATMOS 2000: 195-204 |
1999 |
1 | EE | Gregorio Cappuccino,
Giuseppe Cocorullo:
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.
EUROMICRO 1999: 1204-1208 |