| 2008 |
|---|
| 58 | EE | Chih-Hao Liu,
Chien-Ching Lin,
Hsie-Chia Chang,
Chen-Yi Lee,
Yarsun Hsua:
Multi-mode message passing switch networks applied for QC-LDPC decoder.
ISCAS 2008: 752-755 |
| 57 | EE | Tsu-Ming Liu,
Chen-Yi Lee:
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead.
Signal Processing Systems 50(1): 69-80 (2008) |
| 2007 |
|---|
| 56 | EE | Tsu-Ming Liu,
Sheng-Zen Wang,
Bai-Jue Shieh,
Chen-Yi Lee:
A New Soft Variable Length Decoder for Wireless Video Transmission.
IEEE Trans. Circuits Syst. Video Techn. 17(2): 224-236 (2007) |
| 55 | EE | Tsu-Ming Liu,
Wen-Ping Lee,
Chen-Yi Lee:
An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule.
IEEE Trans. Circuits Syst. Video Techn. 17(7): 937-943 (2007) |
| 54 | EE | Terng-Ren Hsu,
Chien-Ching Lin,
Terng-Yin Hsu,
Chen-Yi Lee:
MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications.
IEICE Transactions 90-A(4): 879-884 (2007) |
| 2006 |
|---|
| 53 | EE | Duo Sheng,
Ching-Che Chung,
Chen-Yi Lee:
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications.
APCCAS 2006: 105-108 |
| 52 | EE | Shao-Ming Sun,
Tsu-Ming Liu,
Chen-Yi Lee:
A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding System.
APCCAS 2006: 1567-1570 |
| 51 | EE | Tsu-Ming Liu,
Chen-Yi Lee:
An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications.
APCCAS 2006: 582-585 |
| 50 | EE | Tsu-Ming Liu,
Ching-Che Chung,
Chen-Yi Lee,
Ting-An Lin,
Sheng-Zen Wang:
Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications.
DAC 2006: 288-289 |
| 49 | EE | Chien-Ching Lin,
Y.-H. Shih,
Hsie-Chia Chang,
Chen-Yi Lee:
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. VLSI Syst. 14(4): 426-430 (2006) |
| 2005 |
|---|
| 48 | EE | Tsu-Ming Liu,
Wen-Ping Lee,
Chen-Yi Lee:
An area-efficient and high-throughput de-blocking filter for multi-standard video applications.
ICIP (3) 2005: 1044-1049 |
| 47 | EE | Ting-An Lin,
Sheng-Zen Wang,
Tsu-Ming Liu,
Chen-Yi Lee:
An H.264/AVC decoder with 4×4-block level pipeline.
ISCAS (2) 2005: 1810-1813 |
| 46 | EE | Ting-An Lin,
Chen-Yi Lee:
Predictive equalizer design for DVB-T system.
ISCAS (2) 2005: 940-943 |
| 45 | EE | Tsu-Ming Liu,
Wen-Ping Lee,
Ting-An Lin,
Chen-Yi Lee:
A memory-efficient deblocking filter for H.264/AVC video coding.
ISCAS (3) 2005: 2140-2143 |
| 44 | EE | Sheng-Zen Wang,
Ting-An Lin,
Tsu-Ming Liu,
Chen-Yi Lee:
A new motion compensation design for H.264/AVC decoder.
ISCAS (5) 2005: 4558-4561 |
| 43 | EE | Pao-Lung Chen,
Ching-Che Chung,
Chen-Yi Lee:
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications.
ISCAS (5) 2005: 4875-4878 |
| 42 | EE | Jui-Yuan Yu,
Ming-Fu Sun,
Terng-Yin Hsu,
Chen-Yi Lee:
A novel technique for I/Q imbalance and CFO compensation in OFDM systems.
ISCAS (6) 2005: 6030-6033 |
| 41 | EE | Pao-Lung Chen,
Chen-Yi Lee:
A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting.
IEICE Transactions 88-A(12): 3554-3563 (2005) |
| 40 | EE | Yen-Kuang Chen,
Stella Kuei-Ann Wen,
Chen-Yi Lee:
Guest Editorial: System-on-a-Chip for Multimedia Systems.
VLSI Signal Processing 41(1): 5-7 (2005) |
| 2004 |
|---|
| 39 | | Tsu-Ming Liu,
Chen-Yi Lee:
A low-complexity soft vlc decoder using performance modeling.
ICIP 2004: 3233-3236 |
| 38 | | Yi-Chen Tseng,
Chien-Ching Lin,
Hsie-Chia Chang,
Chen-Yi Lee:
A power and area efficient multi-mode FEC processor.
ISCAS (2) 2004: 253-256 |
| 37 | | Cheng-Hung Liu,
Bai-Jue Shieh,
Chen-Yi Lee:
A low-power group-based VLD design.
ISCAS (2) 2004: 337-340 |
| 36 | EE | Wen-Hsiao Peng,
Tihao Chiang,
Hsueh-Ming Hang,
Chen-Yi Lee:
Enhanced Stochastic Bit Reshuffling for Fine Granular Scalable Video Coding.
PCM (2) 2004: 521-528 |
| 2003 |
|---|
| 35 | EE | Hsuan-Yu Liu,
Yi-Hsin Yu,
Chien-Jen Hung,
Temg-Yin Hsu,
Chen-Yi Lee:
Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems.
ISCAS (2) 2003: 149-152 |
| 34 | EE | Jhy-Neng Yang,
Yi-Chang Cheng,
Chen-Yi Lee:
A Design of CMOS Broadband Amplifier With High-Q Active Inductor.
IWSOC 2003: 86-89 |
| 33 | EE | Wei-Chang Tsai,
Chun-Ming Huang,
Jiann-Jenn Wang,
Chen-Yi Lee:
Infrastructure for Education and Research of SOC/IP in Taiwan.
MSE 2003: 150- |
| 32 | | Yew-San Lee,
Keng-Khai Ong,
Chen-Yi Lee:
Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission.
IEEE Trans. Circuits Syst. Video Techn. 13(2): 176-181 (2003) |
| 31 | EE | Hsie-Chia Chang,
Chen-Yi Lee:
A Low-Power Design for Reed-Solomon Decoders.
Journal of Circuits, Systems, and Computers 12(2): 159-170 (2003) |
| 30 | EE | Cheng-Hsien Chen,
Chen-Yi Lee:
Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware.
The Visual Computer 19(7-8): 467-479 (2003) |
| 2002 |
|---|
| 29 | | Keng-Khai Ong,
Wei-Hsin Chang,
Yi-Chen Tseng,
Yew-San Lee,
Chen-Yi Lee:
A high throughput low cost context-based adaptive arithmetic codec for multiple standards.
ICIP (1) 2002: 872-875 |
| 28 | | Hung-Kuo Wei,
Yew-San Lee,
Yen-Hsu Shih,
Chen-Yi Lee:
A novel fixed bit plane error resilient image coding for wireless multimedia transmission.
ICIP (3) 2002: 565-568 |
| 27 | EE | Keng-Khai Ong,
Wei-Hsin Chang,
Yi-Chen Tseng,
Yew-San Lee,
Chen-Yi Lee:
A high throughput context-based adaptive arithmetic codec for JPEG2000.
ISCAS (4) 2002: 133-136 |
| 26 | EE | Yew-San Lee,
Cheng-Mou Yu,
Hung-Kuo Wei,
Yen-Hsu Shih,
Chen-Yi Lee:
A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication.
ISCAS (5) 2002: 121-124 |
| 25 | EE | Cheng-Hsien Chen,
Chen-Yi Lee:
Reduce the Memory Bandwidth of 3D Graphics Hardware with a Novel Rasterizer.
Journal of Circuits, Systems, and Computers 11(4): 377-392 (2002) |
| 2001 |
|---|
| 24 | EE | Jin-Jer Jong,
Chen-Yi Lee:
A novel structure for portable digitally controlled oscillator.
ISCAS (1) 2001: 272-275 |
| 23 | EE | Hsie-Chia Chang,
Chen-Yi Lee:
An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm.
ISCAS (2) 2001: 649-652 |
| 22 | EE | F. S. Tsai,
Chen-Yi Lee:
A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system.
ISCAS (4) 2001: 132-135 |
| 21 | EE | Yew-San Lee,
Cheng-Mou Yu,
Chen-Yi Lee:
Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission.
ISCAS (4) 2001: 326-329 |
| 20 | EE | Wei-Hsin Chang,
Yew-San Lee,
Wen-Shiaw Peng,
Chen-Yi Lee:
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme.
ISCAS (4) 2001: 330-333 |
| 19 | EE | Yi-Chuan Liu,
Chung-Cheng Wang,
Terng-Yin Hsu,
Chen-Yi Lee:
A wideband digital frequency synthesizer.
ISCAS (4) 2001: 710-713 |
| 18 | EE | Wei-Hsin Chang,
Shuenn-Der Tzeng,
Chen-Yi Lee:
A novel subcircuit extraction algorithm by recursive identification scheme.
ISCAS (5) 2001: 491-494 |
| 17 | | Bai-Jue Shieh,
Yew-San Lee,
Chen-Yi Lee:
A new approach of group-based VLC codec system with full table programmability.
IEEE Trans. Circuits Syst. Video Techn. 11(2): 210-221 (2001) |
| 2000 |
|---|
| 16 | | Yew-San Lee,
Wei-Shin Chang,
Hsin-Han Ho,
Chen-Yi Lee:
Construction of Error Resilient Synchronization Codeword for Variable-Length Code in Image Transmission.
ICIP 2000 |
| 15 | | Bai-Jue Shieh,
Yew-San Lee,
Chen-Yi Lee:
A high-throughput memory-based VLC decoder with codeword boundary prediction.
IEEE Trans. Circuits Syst. Video Techn. 10(8): 1514-1521 (2000) |
| 1999 |
|---|
| 14 | | Yuan-Hau Yeh,
Chen-Yi Lee:
A New Anti-Aliasing Algorithm for Computer Graphics Images.
ICIP (2) 1999: 442-446 |
| 13 | EE | Wen-Shiaw Peng,
Chen-Yi Lee:
An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform.
ICIP (2) 1999: 754-758 |
| 12 | | Cheng-Hsien Chen,
Chen-Yi Lee:
A Cost-Effective Lighting Processor for 3D Graphics Application.
ICIP (2) 1999: 792-796 |
| 11 | EE | Yuan-Hau Yeh,
Chen-Yi Lee:
Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms.
IEEE Trans. VLSI Syst. 7(3): 345-358 (1999) |
| 1997 |
|---|
| 10 | EE | Yuan-Hau Yeh,
Chen-Yi Lee:
Buffer size optimization for full-search block matching algorithms.
ASAP 1997: 76-85 |
| 9 | EE | Chen-Yi Lee,
Mei-Cheng Lu:
An Efficient VLSI Architecture for Full-Search Block Matching Algorithms.
VLSI Signal Processing 15(3): 275-282 (1997) |
| 1995 |
|---|
| 8 | | Yen-Juan Chao,
Chen-Yi Lee:
A New Multi-Path Tree-Search FSVQ Architecture for Image/Video Sequence Coding.
ISCAS 1995: 1628-1631 |
| 7 | | Eddie G. Tzeng,
Chen-Yi Lee:
An Efficient Memory Architecture for Motion Estimation Processor Design.
ISCAS 1995: 712-715 |
| 6 | EE | Chen-Yi Lee,
Jer-Min Tsai:
A shift register architecture for high-speed data sorting.
VLSI Signal Processing 11(3): 273-280 (1995) |
| 1994 |
|---|
| 5 | | Ren-Yang Yang,
Chen-Yi Lee:
High-Throughput Data Compressor Designs Using Content Addressable Memory.
ISCAS 1994: 147-150 |
| 4 | | Wen-Wei Yang,
Li-Fu Jeng,
Chen-Yi Lee:
Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy.
ISCAS 1994: 165-168 |
| 3 | | Shi-Chou Juan,
Yen-Jean Chao,
Chen-Yi Lee:
Finite State Vector Quantization with Multi-Path Tree Search Strategy for Image/Video Coding.
ISCAS 1994: 181-184 |
| 1993 |
|---|
| 2 | | Chen-Yi Lee,
Shih-Chou Juan,
Wen-Wei Yang:
An area-efficient maximum/minimum detection circuit for digital and video signal processing.
ISCAS 1993: 223-226 |
| 1990 |
|---|
| 1 | | Chen-Yi Lee,
Francky Catthoor,
Hugo De Man:
Efficient VLSI Architectures for a High-Performance Digital Image Communication System.
IEEE Journal on Selected Areas in Communications 8(8): 1481-1491 (1990) |
