| |
| 2006 | ||
|---|---|---|
| 3 | EE | Thara Rejimon, Sanjukta Bhanja: Wide Limited Switch Dynamic Logic Circuit Implementations. VLSI Design 2006: 94-99 |
| 2 | EE | Thara Rejimon, Sanjukta Bhanja: A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis. IEEE Trans. VLSI Syst. 14(10): 1130-1139 (2006) |
| 2005 | ||
| 1 | EE | Thara Rejimon, Sanjukta Bhanja: An Accurate Probalistic Model for Error Detection. VLSI Design 2005: 717-722 |
| 1 | Sanjukta Bhanja | [1] [2] [3] |